qemu/target
Conor Dooley 1c8e491c45 target/riscv: support new isa extension detection devicetree properties
A few months ago I submitted a patch to various lists, deprecating
"riscv,isa" with a lengthy commit message [0] that is now commit
aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") in the Linux
kernel tree. Primarily, the goal was to replace "riscv,isa" with a new
set of properties that allowed for strictly defining the meaning of
various extensions, where "riscv,isa" was tied to whatever definitions
inflicted upon us by the ISA manual, which have seen some variance over
time.

Two new properties were introduced: "riscv,isa-base" and
"riscv,isa-extensions". The former is a simple string to communicate the
base ISA implemented by a hart and the latter an array of strings used
to communicate the set of ISA extensions supported, per the definitions
of each substring in extensions.yaml [1]. A beneficial side effect was
also the ability to define vendor extensions in a more "official" way,
as the ISA manual and other RVI specifications only covered the format
for vendor extensions in the ISA string, but not the meaning of vendor
extensions, for obvious reasons.

Add support for setting these two new properties in the devicetrees for
the various devicetree platforms supported by QEMU for RISC-V. The Linux
kernel already supports parsing ISA extensions from these new
properties, and documenting them in the dt-binding is a requirement for
new extension detection being added to the kernel.

A side effect of the implementation is that the meaning for elements in
"riscv,isa" and in "riscv,isa-extensions" are now tied together as they
are constructed from the same source. The same applies to the ISA string
provided in ACPI tables, but there does not appear to be any strict
definitions of meanings in ACPI land either.

Link: https://lore.kernel.org/qemu-riscv/20230702-eats-scorebook-c951f170d29f@spud/ [0]
Link: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/riscv/extensions.yaml [1]
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240124-unvarying-foothold-9dde2aaf95d4@spud>
[ Changes by AF:
 - Rebase on recent changes
]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-02-09 20:43:14 +10:00
..
alpha target/alpha: Use TCG_COND_TSTNE for gen_fold_mzero 2024-02-03 23:43:50 +00:00
arm tests/tcg: Fix multiarch/gdbstub/prot-none.py 2024-02-03 13:31:45 +00:00
avr include/exec: Implement cpu_mmu_index generically 2024-02-03 16:46:10 +10:00
cris include/exec: Change cpu_mmu_index argument to CPUState 2024-02-03 16:46:10 +10:00
hexagon include/exec: Implement cpu_mmu_index generically 2024-02-03 16:46:10 +10:00
hppa include/exec: Change cpu_mmu_index argument to CPUState 2024-02-03 16:46:10 +10:00
i386 include/exec: Change cpu_mmu_index argument to CPUState 2024-02-03 16:46:10 +10:00
loongarch include/exec: Change cpu_mmu_index argument to CPUState 2024-02-03 16:46:10 +10:00
m68k target/m68k: Use TCG_COND_TST{EQ,NE} in gen_fcc_cond 2024-02-03 23:43:50 +00:00
microblaze include/exec: Change cpu_mmu_index argument to CPUState 2024-02-03 16:46:10 +10:00
mips include/exec: Implement cpu_mmu_index generically 2024-02-03 16:46:10 +10:00
nios2 include/exec: Change cpu_mmu_index argument to CPUState 2024-02-03 16:46:10 +10:00
openrisc include/exec: Change cpu_mmu_index argument to CPUState 2024-02-03 16:46:10 +10:00
ppc target/ppc/cpu-models: Rename power5+ and power7+ for new QOM naming rules 2024-02-05 14:21:21 +01:00
riscv target/riscv: support new isa extension detection devicetree properties 2024-02-09 20:43:14 +10:00
rx include/exec: Implement cpu_mmu_index generically 2024-02-03 16:46:10 +10:00
s390x tcg: Introduce TCG_COND_TST{EQ,NE} 2024-02-08 16:08:42 +00:00
sh4 include/exec: Implement cpu_mmu_index generically 2024-02-03 16:46:10 +10:00
sparc target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc 2024-02-03 23:43:50 +00:00
tricore include/exec: Change cpu_mmu_index argument to CPUState 2024-02-03 16:46:10 +10:00
xtensa include/exec: Change cpu_mmu_index argument to CPUState 2024-02-03 16:46:10 +10:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target: Make qemu_target_page_mask() available for *-user 2024-01-29 21:04:10 +10:00
target-common.c target: Make qemu_target_page_mask() available for *-user 2024-01-29 21:04:10 +10:00