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include/exec: Implement cpu_mmu_index generically

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For user-only mode, use MMU_USER_IDX.
For system mode, use CPUClass.mmu_index.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-01-29 11:37:54 +10:00
parent 68283ff4b4
commit a120d32097
31 changed files with 34 additions and 133 deletions
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4
include/exec/cpu-all.h
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@ -311,6 +311,10 @@ CPUArchState *cpu_copy(CPUArchState *env);
#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2))
#define TLB_WATCHPOINT 0
static inline int cpu_mmu_index(CPUArchState *env, bool ifetch)
{
return MMU_USER_IDX;
}
#else
/*

22
include/exec/cpu-common.h
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@ -8,6 +8,7 @@
#include "exec/hwaddr.h"
#endif
#include "hw/core/cpu.h"
#include "tcg/debug-assert.h"
#define EXCP_INTERRUPT 0x10000 /* async interruption */
#define EXCP_HLT 0x10001 /* hlt instruction reached */
@ -262,4 +263,25 @@ static inline CPUState *env_cpu(CPUArchState *env)
return (void *)env - sizeof(CPUState);
}
#ifndef CONFIG_USER_ONLY
/**
* cpu_mmu_index:
* @env: The cpu environment
* @ifetch: True for code access, false for data access.
*
* Return the core mmu index for the current translation regime.
* This function is used by generic TCG code paths.
*
* The user-only version of this function is inline in cpu-all.h,
* where it always returns MMU_USER_IDX.
*/
static inline int cpu_mmu_index(CPUArchState *env, bool ifetch)
{
CPUState *cs = env_cpu(env);
int ret = cs->cc->mmu_index(cs, ifetch);
tcg_debug_assert(ret >= 0 && ret < NB_MMU_MODES);
return ret;
}
#endif /* !CONFIG_USER_ONLY */
#endif /* CPU_COMMON_H */

5
target/alpha/cpu.h
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@ -398,11 +398,6 @@ static inline int alpha_env_mmu_index(CPUAlphaState *env)
return ret;
}
static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch)
{
return alpha_env_mmu_index(env);
}
enum {
IR_V0 = 0,
IR_T0 = 1,

13
target/arm/cpu.h
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@ -3240,19 +3240,6 @@ FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1)
#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH)
#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH)
/**
* cpu_mmu_index:
* @env: The cpu environment
* @ifetch: True for code access, false for data access.
*
* Return the core mmu index for the current translation regime.
* This function is used by generic TCG code paths.
*/
static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
{
return EX_TBFLAG_ANY(env->hflags, MMUIDX);
}
/**
* sve_vq
* @env: the cpu context

5
target/avr/cpu.h
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@ -184,11 +184,6 @@ static inline void set_avr_feature(CPUAVRState *env, int feature)
env->features |= (1U << feature);
}
static inline int cpu_mmu_index(CPUAVRState *env, bool ifetch)
{
return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX;
}
void avr_cpu_tcg_init(void);
int cpu_avr_exec(CPUState *cpu);

4
target/cris/cpu.h
View File

@ -260,10 +260,6 @@ enum {
/* MMU modes definitions */
#define MMU_USER_IDX 1
static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch)
{
return !!(env->pregs[PR_CCS] & U_FLAG);
}
/* Support function regs. */
#define SFR_RW_GC_CFG 0][0

9
target/hexagon/cpu.h
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@ -146,15 +146,6 @@ static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc,
*flags = hex_flags;
}
static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch)
{
#ifdef CONFIG_USER_ONLY
return MMU_USER_IDX;
#else
#error System mode not supported on Hexagon yet
#endif
}
typedef HexagonCPU ArchCPU;
void hexagon_translate_init(void);

2
target/hppa/cpu.c
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@ -94,7 +94,7 @@ static bool hppa_cpu_has_work(CPUState *cs)
return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
}
int hppa_cpu_mmu_index(CPUState *cs, bool ifetch)
static int hppa_cpu_mmu_index(CPUState *cs, bool ifetch)
{
CPUHPPAState *env = cpu_env(cs);

10
target/hppa/cpu.h
View File

@ -281,16 +281,6 @@ static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env)
return hppa_is_pa20(env) ? 0 : PA10_BTLB_FIXED + PA10_BTLB_VARIABLE;
}
int hppa_cpu_mmu_index(CPUState *cs, bool ifetch);
static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
{
#ifdef CONFIG_USER_ONLY
return MMU_USER_IDX;
#else
return hppa_cpu_mmu_index(env_cpu(env), ifetch);
#endif
}
void hppa_translate_init(void);
#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU

2
target/i386/cpu.c
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@ -7720,7 +7720,7 @@ static bool x86_cpu_has_work(CPUState *cs)
return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
}
int x86_cpu_mmu_index(CPUState *cs, bool ifetch)
static int x86_cpu_mmu_index(CPUState *cs, bool ifetch)
{
CPUX86State *env = cpu_env(cs);

6
target/i386/cpu.h
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@ -2315,12 +2315,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env)
#include "hw/i386/apic.h"
#endif
int x86_cpu_mmu_index(CPUState *cs, bool ifetch);
static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
{
return x86_cpu_mmu_index(env_cpu(env), ifetch);
}
static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc,
uint64_t *cs_base, uint32_t *flags)
{

2
target/loongarch/cpu.c
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@ -375,7 +375,7 @@ static bool loongarch_cpu_has_work(CPUState *cs)
#endif
}
int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch)
static int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch)
{
CPULoongArchState *env = cpu_env(cs);

10
target/loongarch/cpu.h
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@ -408,16 +408,6 @@ struct LoongArchCPUClass {
#define MMU_USER_IDX MMU_PLV_USER
#define MMU_DA_IDX 4
int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch);
static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
{
#ifdef CONFIG_USER_ONLY
return MMU_USER_IDX;
#else
return loongarch_cpu_mmu_index(env_cpu(env), ifetch);
#endif
}
static inline bool is_la64(CPULoongArchState *env)
{
return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64;

4
target/m68k/cpu.h
View File

@ -577,10 +577,6 @@ enum {
/* MMU modes definitions */
#define MMU_KERNEL_IDX 0
#define MMU_USER_IDX 1
static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
{
return (env->sr & SR_S) == 0 ? 1 : 0;
}
bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,

2
target/microblaze/cpu.c
View File

@ -118,7 +118,7 @@ static bool mb_cpu_has_work(CPUState *cs)
return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
}
int mb_cpu_mmu_index(CPUState *cs, bool ifetch)
static int mb_cpu_mmu_index(CPUState *cs, bool ifetch)
{
CPUMBState *env = cpu_env(cs);
MicroBlazeCPU *cpu = env_archcpu(env);

6
target/microblaze/cpu.h
View File

@ -434,12 +434,6 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
MemTxResult response, uintptr_t retaddr);
#endif
int mb_cpu_mmu_index(CPUState *cs, bool ifetch);
static inline int cpu_mmu_index(CPUMBState *env, bool ifetch)
{
return mb_cpu_mmu_index(env_cpu(env), ifetch);
}
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_mb_cpu;
#endif

5
target/mips/cpu.h
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@ -1260,11 +1260,6 @@ static inline int mips_env_mmu_index(CPUMIPSState *env)
return hflags_mmu_index(env->hflags);
}
static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
{
return mips_env_mmu_index(env);
}
#include "exec/cpu-all.h"
/* Exceptions */

2
target/nios2/cpu.c
View File

@ -57,7 +57,7 @@ static bool nios2_cpu_has_work(CPUState *cs)
return cs->interrupt_request & CPU_INTERRUPT_HARD;
}
int nios2_cpu_mmu_index(CPUState *cs, bool ifetch)
static int nios2_cpu_mmu_index(CPUState *cs, bool ifetch)
{
return (cpu_env(cs)->ctrl[CR_STATUS] & CR_STATUS_U
? MMU_USER_IDX : MMU_SUPERVISOR_IDX);

6
target/nios2/cpu.h
View File

@ -286,12 +286,6 @@ FIELD(TBFLAGS, CRS0, 0, 1) /* Set if CRS == 0. */
FIELD(TBFLAGS, U, 1, 1) /* Overlaps CR_STATUS_U */
FIELD(TBFLAGS, R0_0, 2, 1) /* Set if R0 == 0. */
int nios2_cpu_mmu_index(CPUState *cs, bool ifetch);
static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch)
{
return nios2_cpu_mmu_index(env_cpu(env), ifetch);
}
static inline void cpu_get_tb_cpu_state(CPUNios2State *env, vaddr *pc,
uint64_t *cs_base, uint32_t *flags)
{

2
target/openrisc/cpu.c
View File

@ -68,7 +68,7 @@ static bool openrisc_cpu_has_work(CPUState *cs)
CPU_INTERRUPT_TIMER);
}
int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch)
static int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch)
{
CPUOpenRISCState *env = cpu_env(cs);

6
target/openrisc/cpu.h
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@ -361,12 +361,6 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc,
| (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE));
}
int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch);
static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch)
{
return openrisc_cpu_mmu_index(env_cpu(env), ifetch);
}
static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env)
{
return (env->sr

5
target/ppc/cpu.h
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@ -1633,11 +1633,6 @@ static inline int ppc_env_mmu_index(CPUPPCState *env, bool ifetch)
#endif
}
static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch)
{
return ppc_env_mmu_index(env, ifetch);
}
/* Compatibility modes */
#if defined(TARGET_PPC64)
bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,

2
target/riscv/cpu.h
View File

@ -507,8 +507,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
bool probe, uintptr_t retaddr);
char *riscv_isa_string(RISCVCPU *cpu);
#define cpu_mmu_index riscv_env_mmu_index
#ifndef CONFIG_USER_ONLY
void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
vaddr addr, unsigned size,

5
target/rx/cpu.h
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@ -158,11 +158,6 @@ static inline void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc,
*flags = FIELD_DP32(*flags, PSW, U, env->psw_u);
}
static inline int cpu_mmu_index(CPURXState *env, bool ifetch)
{
return 0;
}
static inline uint32_t rx_cpu_pack_psw(CPURXState *env)
{
uint32_t psw = 0;

2
target/s390x/cpu.h
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@ -412,8 +412,6 @@ static inline int s390x_env_mmu_index(CPUS390XState *env, bool ifetch)
#endif
}
#define cpu_mmu_index s390x_env_mmu_index
#ifdef CONFIG_TCG
#include "tcg/tcg_s390x.h"

2
target/sh4/cpu.c
View File

@ -89,7 +89,7 @@ static bool superh_cpu_has_work(CPUState *cs)
return cs->interrupt_request & CPU_INTERRUPT_HARD;
}
int sh4_cpu_mmu_index(CPUState *cs, bool ifetch)
static int sh4_cpu_mmu_index(CPUState *cs, bool ifetch)
{
CPUSH4State *env = cpu_env(cs);

6
target/sh4/cpu.h
View File

@ -370,12 +370,6 @@ static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr)
env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T));
}
int sh4_cpu_mmu_index(CPUState *cs, bool ifetch);
static inline int cpu_mmu_index(CPUSH4State *env, bool ifetch)
{
return sh4_cpu_mmu_index(env_cpu(env), ifetch);
}
static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc,
uint64_t *cs_base, uint32_t *flags)
{

2
target/sparc/cpu.c
View File

@ -718,7 +718,7 @@ static bool sparc_cpu_has_work(CPUState *cs)
cpu_interrupts_enabled(env);
}
int sparc_cpu_mmu_index(CPUState *cs, bool ifetch)
static int sparc_cpu_mmu_index(CPUState *cs, bool ifetch)
{
CPUSPARCState *env = cpu_env(cs);

6
target/sparc/cpu.h
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@ -749,12 +749,6 @@ trap_state* cpu_tsptr(CPUSPARCState* env);
#define TB_FLAG_HYPER (1 << 7)
#define TB_FLAG_ASI_SHIFT 24
int sparc_cpu_mmu_index(CPUState *cs, bool ifetch);
static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch)
{
return sparc_cpu_mmu_index(env_cpu(env), ifetch);
}
static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *pflags)
{

5
target/tricore/cpu.h
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@ -246,11 +246,6 @@ void fpu_set_state(CPUTriCoreState *env);
#define MMU_USER_IDX 2
static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)
{
return 0;
}
#include "exec/cpu-all.h"
FIELD(TB_FLAGS, PRIV, 0, 2)

5
target/xtensa/cpu.h
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@ -713,11 +713,6 @@ static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
/* MMU modes definitions */
#define MMU_USER_IDX 3
static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
{
return xtensa_get_cring(env);
}
#define XTENSA_TBFLAG_RING_MASK 0x3
#define XTENSA_TBFLAG_EXCM 0x4
#define XTENSA_TBFLAG_LITBASE 0x8