ce2918cbc3
The qemu coding standard is to use CamelCase for type and structure names,
and the pseries code follows that... sort of. There are quite a lot of
places where we bend the rules in order to preserve the capitalization of
internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR".
That was a bad idea - it frequently leads to names ending up with hard to
read clusters of capital letters, and means they don't catch the eye as
type identifiers, which is kind of the point of the CamelCase convention in
the first place.
In short, keeping type identifiers look like CamelCase is more important
than preserving standard capitalization of internal "words". So, this
patch renames a heap of spapr internal type names to a more standard
CamelCase.
In addition to case changes, we also make some other identifier renames:
VIOsPAPR* -> SpaprVio*
The reverse word ordering was only ever used to mitigate the capital
cluster, so revert to the natural ordering.
VIOsPAPRVTYDevice -> SpaprVioVty
VIOsPAPRVLANDevice -> SpaprVioVlan
Brevity, since the "Device" didn't add useful information
sPAPRDRConnector -> SpaprDrc
sPAPRDRConnectorClass -> SpaprDrcClass
Brevity, and makes it clearer this is the same thing as a "DRC"
mentioned in many other places in the code
This is 100% a mechanical search-and-replace patch. It will, however,
conflict with essentially any and all outstanding patches touching the
spapr code.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
54 lines
1.4 KiB
C
54 lines
1.4 KiB
C
/*
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* QEMU PowerPC sPAPR XIVE interrupt controller model
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*
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* Copyright (c) 2017-2018, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef PPC_SPAPR_XIVE_H
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#define PPC_SPAPR_XIVE_H
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#include "hw/ppc/xive.h"
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#define TYPE_SPAPR_XIVE "spapr-xive"
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#define SPAPR_XIVE(obj) OBJECT_CHECK(SpaprXive, (obj), TYPE_SPAPR_XIVE)
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typedef struct SpaprXive {
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XiveRouter parent;
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/* Internal interrupt source for IPIs and virtual devices */
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XiveSource source;
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hwaddr vc_base;
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/* END ESB MMIOs */
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XiveENDSource end_source;
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hwaddr end_base;
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/* DT */
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gchar *nodename;
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/* Routing table */
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XiveEAS *eat;
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uint32_t nr_irqs;
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XiveEND *endt;
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uint32_t nr_ends;
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/* TIMA mapping address */
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hwaddr tm_base;
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MemoryRegion tm_mmio;
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} SpaprXive;
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bool spapr_xive_irq_claim(SpaprXive *xive, uint32_t lisn, bool lsi);
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bool spapr_xive_irq_free(SpaprXive *xive, uint32_t lisn);
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void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon);
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void spapr_xive_hcall_init(SpaprMachineState *spapr);
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void spapr_dt_xive(SpaprMachineState *spapr, uint32_t nr_servers, void *fdt,
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uint32_t phandle);
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void spapr_xive_set_tctx_os_cam(XiveTCTX *tctx);
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void spapr_xive_mmio_set_enabled(SpaprXive *xive, bool enable);
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#endif /* PPC_SPAPR_XIVE_H */
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