ce2918cbc3
The qemu coding standard is to use CamelCase for type and structure names, and the pseries code follows that... sort of. There are quite a lot of places where we bend the rules in order to preserve the capitalization of internal acronyms like "PHB", "TCE", "DIMM" and most commonly "sPAPR". That was a bad idea - it frequently leads to names ending up with hard to read clusters of capital letters, and means they don't catch the eye as type identifiers, which is kind of the point of the CamelCase convention in the first place. In short, keeping type identifiers look like CamelCase is more important than preserving standard capitalization of internal "words". So, this patch renames a heap of spapr internal type names to a more standard CamelCase. In addition to case changes, we also make some other identifier renames: VIOsPAPR* -> SpaprVio* The reverse word ordering was only ever used to mitigate the capital cluster, so revert to the natural ordering. VIOsPAPRVTYDevice -> SpaprVioVty VIOsPAPRVLANDevice -> SpaprVioVlan Brevity, since the "Device" didn't add useful information sPAPRDRConnector -> SpaprDrc sPAPRDRConnectorClass -> SpaprDrcClass Brevity, and makes it clearer this is the same thing as a "DRC" mentioned in many other places in the code This is 100% a mechanical search-and-replace patch. It will, however, conflict with essentially any and all outstanding patches touching the spapr code. Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
73 lines
2.7 KiB
C
73 lines
2.7 KiB
C
/*
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* QEMU PowerPC sPAPR IRQ backend definitions
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*
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* Copyright (c) 2018, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef HW_SPAPR_IRQ_H
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#define HW_SPAPR_IRQ_H
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/*
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* IRQ range offsets per device type
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*/
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#define SPAPR_IRQ_IPI 0x0
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#define SPAPR_IRQ_EPOW 0x1000 /* XICS_IRQ_BASE offset */
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#define SPAPR_IRQ_HOTPLUG 0x1001
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#define SPAPR_IRQ_VIO 0x1100 /* 256 VIO devices */
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#define SPAPR_IRQ_PCI_LSI 0x1200 /* 32+ PHBs devices */
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#define SPAPR_IRQ_MSI 0x1300 /* Offset of the dynamic range covered
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* by the bitmap allocator */
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typedef struct SpaprMachineState SpaprMachineState;
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void spapr_irq_msi_init(SpaprMachineState *spapr, uint32_t nr_msis);
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int spapr_irq_msi_alloc(SpaprMachineState *spapr, uint32_t num, bool align,
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Error **errp);
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void spapr_irq_msi_free(SpaprMachineState *spapr, int irq, uint32_t num);
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void spapr_irq_msi_reset(SpaprMachineState *spapr);
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typedef struct SpaprIrq {
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uint32_t nr_irqs;
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uint32_t nr_msis;
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uint8_t ov5;
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void (*init)(SpaprMachineState *spapr, int nr_irqs, Error **errp);
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int (*claim)(SpaprMachineState *spapr, int irq, bool lsi, Error **errp);
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void (*free)(SpaprMachineState *spapr, int irq, int num);
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qemu_irq (*qirq)(SpaprMachineState *spapr, int irq);
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void (*print_info)(SpaprMachineState *spapr, Monitor *mon);
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void (*dt_populate)(SpaprMachineState *spapr, uint32_t nr_servers,
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void *fdt, uint32_t phandle);
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void (*cpu_intc_create)(SpaprMachineState *spapr, PowerPCCPU *cpu,
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Error **errp);
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int (*post_load)(SpaprMachineState *spapr, int version_id);
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void (*reset)(SpaprMachineState *spapr, Error **errp);
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void (*set_irq)(void *opaque, int srcno, int val);
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const char *(*get_nodename)(SpaprMachineState *spapr);
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} SpaprIrq;
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extern SpaprIrq spapr_irq_xics;
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extern SpaprIrq spapr_irq_xics_legacy;
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extern SpaprIrq spapr_irq_xive;
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extern SpaprIrq spapr_irq_dual;
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void spapr_irq_init(SpaprMachineState *spapr, Error **errp);
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int spapr_irq_claim(SpaprMachineState *spapr, int irq, bool lsi, Error **errp);
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void spapr_irq_free(SpaprMachineState *spapr, int irq, int num);
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qemu_irq spapr_qirq(SpaprMachineState *spapr, int irq);
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int spapr_irq_post_load(SpaprMachineState *spapr, int version_id);
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void spapr_irq_reset(SpaprMachineState *spapr, Error **errp);
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int spapr_irq_get_phandle(SpaprMachineState *spapr, void *fdt, Error **errp);
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/*
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* XICS legacy routines
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*/
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int spapr_irq_find(SpaprMachineState *spapr, int num, bool align, Error **errp);
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#define spapr_irq_findone(spapr, errp) spapr_irq_find(spapr, 1, false, errp)
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#endif
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