qemu/target/arm
Peter Maydell ebfe27c593 target/arm: Tighten up Thumb decode where new v8M insns will be
Tighten up the T32 decoder in the places where new v8M instructions
will be:
 * TT/TTT/TTA/TTAT are in what was nominally LDREX/STREX r15, ...
   which is UNPREDICTABLE:
   make the UNPREDICTABLE behaviour be to UNDEF
 * BXNS/BLXNS are distinguished from BX/BLX via the low 3 bits,
   which in previous architectural versions are SBZ:
   enforce the SBZ via UNDEF rather than ignoring it, and move
   the "ARCH(5)" UNDEF case up so we don't leak a TCG temporary
 * SG is in the encoding which would be LDRD/STRD with rn = r15;
   this is UNPREDICTABLE and we currently UNDEF:
   move this check further up the code so that we don't leak
   TCG temporaries in the UNDEF case and have a better place
   to put the SG decode.

This means that if a v8M binary is accidentally run on v7M
or if a test case hits something that we haven't implemented
yet the behaviour will be obvious (UNDEF) rather than obscure
(plough on treating it as a different instruction).

In the process, add some comments about the instruction patterns
at these points in the decode. Our Thumb and ARM decoders are
very difficult to understand currently, but gradually adding
comments like this should help to clarify what exactly has
been decoded when.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1501692241-23310-5-git-send-email-peter.maydell@linaro.org
2017-09-04 15:21:51 +01:00
..
arch_dump.c
arm_ldst.h Fix Thumb-1 BE32 execution and disassembly. 2017-02-07 18:29:59 +00:00
arm-powerctl.c target-arm/powerctl: defer cpu reset work to CPU context 2017-02-24 10:32:46 +00:00
arm-powerctl.h target-arm/powerctl: defer cpu reset work to CPU context 2017-02-24 10:32:46 +00:00
arm-semi.c
cpu64.c target-arm: Enable EL2 feature bit on A53 and A57 2017-01-20 11:15:10 +00:00
cpu-qom.h
cpu.c target/arm: Move PMSAv7 reset into arm_cpu_reset() so M profile MPUs get reset 2017-07-31 13:09:52 +01:00
cpu.h arm: replace cpu_arm_init() with cpu_generic_init() 2017-09-01 11:54:24 -03:00
crypto_helper.c
gdbstub64.c
gdbstub.c
helper-a64.c target-arm: Use clrsb helper 2017-01-10 08:47:48 -08:00
helper-a64.h target-arm: Use clrsb helper 2017-01-10 08:47:48 -08:00
helper.c target/arm: Consolidate PMSA handling in get_phys_addr() 2017-09-04 15:21:51 +01:00
helper.h target-arm: Use clz opcode 2017-01-10 08:06:11 -08:00
internals.h target/arm: Use MMUAccessType enum rather than int 2017-09-04 15:21:51 +01:00
iwmmxt_helper.c
kvm32.c
kvm64.c arm/kvm: Remove trailing newlines from error_report() 2017-04-20 17:39:17 +01:00
kvm_arm.h
kvm-consts.h arm: add trailing ; after MISMATCH_CHECK 2017-02-01 03:37:18 +02:00
kvm-stub.c
kvm.c ARM: KVM: Enable in-kernel timers with user space gic 2017-07-11 11:21:26 +01:00
machine.c target/arm: Migrate MPU_RNR register state for M profile cores 2017-07-31 13:09:52 +01:00
Makefile.objs
monitor.c
neon_helper.c
op_addsub.h
op_helper.c target/arm: Don't trap WFI/WFE for M profile 2017-09-04 15:21:51 +01:00
psci.c shutdown: Add source information to SHUTDOWN and RESET 2017-05-23 13:28:17 +02:00
trace-events trace-events: fix code style: print 0x before hex numbers 2017-08-01 12:13:07 +01:00
translate-a64.c target/arm: Require alignment for load exclusive 2017-08-15 17:38:44 +01:00
translate.c target/arm: Tighten up Thumb decode where new v8M insns will be 2017-09-04 15:21:51 +01:00
translate.h tcg: Pass generic CPUState to gen_intermediate_code() 2017-07-19 14:45:16 -07:00