qemu/target
Peter Maydell ebfe27c593 target/arm: Tighten up Thumb decode where new v8M insns will be
Tighten up the T32 decoder in the places where new v8M instructions
will be:
 * TT/TTT/TTA/TTAT are in what was nominally LDREX/STREX r15, ...
   which is UNPREDICTABLE:
   make the UNPREDICTABLE behaviour be to UNDEF
 * BXNS/BLXNS are distinguished from BX/BLX via the low 3 bits,
   which in previous architectural versions are SBZ:
   enforce the SBZ via UNDEF rather than ignoring it, and move
   the "ARCH(5)" UNDEF case up so we don't leak a TCG temporary
 * SG is in the encoding which would be LDRD/STRD with rn = r15;
   this is UNPREDICTABLE and we currently UNDEF:
   move this check further up the code so that we don't leak
   TCG temporaries in the UNDEF case and have a better place
   to put the SG decode.

This means that if a v8M binary is accidentally run on v7M
or if a test case hits something that we haven't implemented
yet the behaviour will be obvious (UNDEF) rather than obscure
(plough on treating it as a different instruction).

In the process, add some comments about the instruction patterns
at these points in the decode. Our Thumb and ARM decoders are
very difficult to understand currently, but gradually adding
comments like this should help to clarify what exactly has
been decoded when.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1501692241-23310-5-git-send-email-peter.maydell@linaro.org
2017-09-04 15:21:51 +01:00
..
alpha alpha: replace cpu_alpha_init() with cpu_generic_init() 2017-09-01 11:54:24 -03:00
arm target/arm: Tighten up Thumb decode where new v8M insns will be 2017-09-04 15:21:51 +01:00
cris cris: replace cpu_cris_init() with cpu_generic_init() 2017-09-01 11:54:24 -03:00
hppa hppa: replace cpu_hppa_init() with cpu_generic_init() 2017-09-01 11:54:24 -03:00
i386 QAPI patches for 2017-09-01 2017-09-04 13:28:09 +01:00
lm32 lm32: replace cpu_lm32_init() with cpu_generic_init() 2017-09-01 11:54:25 -03:00
m68k m68k: replace cpu_m68k_init() with cpu_generic_init() 2017-09-01 11:54:24 -03:00
microblaze microblaze: replace cpu_mb_init() with cpu_generic_init() 2017-09-01 11:54:24 -03:00
mips target/mips: Fix RDHWR CC with icount 2017-08-02 22:18:13 +01:00
moxie moxie: replace cpu_moxie_init() with cpu_generic_init() 2017-09-01 11:54:25 -03:00
nios2 nios2: replace cpu_nios2_init() with cpu_generic_init() 2017-09-01 11:54:24 -03:00
openrisc openrisc: replace cpu_openrisc_init() with cpu_generic_init() 2017-09-01 11:54:25 -03:00
ppc ppc: replace cpu_ppc_init() with cpu_generic_init() 2017-09-01 11:54:25 -03:00
s390x s390x: replace cpu_s390x_init() with cpu_generic_init() 2017-09-01 11:54:24 -03:00
sh4 sh4: replace cpu_sh4_init() with cpu_generic_init() 2017-09-01 11:54:24 -03:00
sparc sparc: replace cpu_sparc_init() with cpu_generic_init() 2017-09-01 11:54:24 -03:00
tilegx tilegx: replace cpu_tilegx_init() with cpu_generic_init() 2017-09-01 11:54:24 -03:00
tricore tricore: replace cpu_tricore_init() with cpu_generic_init() 2017-09-01 11:54:24 -03:00
unicore32 unicore32: replace uc32_cpu_init() with cpu_generic_init() 2017-09-01 11:54:25 -03:00
xtensa xtensa: replace cpu_xtensa_init() with cpu_generic_init() 2017-09-01 11:54:24 -03:00