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Travis Geiselbrecht e573a7f325 target/riscv: line up all of the registers in the info register dump 
Ensure the columns for all of the register names and values line up.
No functional change, just a minor tweak to the output.

Signed-off-by: Travis Geiselbrecht <travisg@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211009055019.545153-1-travisg@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22 07:47:51 +10:00
..
insn_trans
target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v
2021-10-22 07:47:51 +10:00
arch_dump.c
target-riscv: support QMP dump-guest-memory
2021-03-04 09:43:29 -05:00
bitmanip_helper.c
target/riscv: Add rev8 instruction, removing grev/grevi
2021-10-07 08:41:33 +10:00
cpu_bits.h
target/riscv: csr: Rename HCOUNTEREN_CY and friends
2021-09-21 12:10:47 +10:00
cpu_helper.c
target/riscv: Backup/restore mstatus.SD bit when virtual register swapped
2021-09-21 12:10:22 +10:00
cpu_user.h
…
cpu-param.h
target/riscv: Add a virtualised MMU Mode
2020-11-09 15:08:45 -08:00
cpu.c
target/riscv: line up all of the registers in the info register dump
2021-10-22 07:47:51 +10:00
cpu.h
target/riscv: Set mstatus_hs.[SD|FS] bits if Clean and V=1 in mark_fs_dirty()
2021-10-07 08:41:33 +10:00
csr.c
target/riscv: csr: Rename HCOUNTEREN_CY and friends
2021-09-21 12:10:47 +10:00
fpu_helper.c
target/riscv: Consolidate RV32/64 32-bit instructions
2021-05-11 20:02:07 +10:00
gdbstub.c
target/riscv: gdbstub: Fix dynamic CSR XML generation
2021-06-24 05:00:12 -07:00
helper.h
target/riscv: Add rev8 instruction, removing grev/grevi
2021-10-07 08:41:33 +10:00
insn16.decode
target/riscv: Consolidate RV32/64 16-bit instructions
2021-05-11 20:02:07 +10:00
insn32.decode
target/riscv: Remove RVB (replaced by Zb[abcs])
2021-10-07 08:41:33 +10:00
instmap.h
…
internals.h
target/riscv: Add basic vmstate description of CPU
2020-11-03 07:17:23 -08:00
Kconfig
meson: Introduce target-specific Kconfig
2021-07-09 18:21:34 +02:00
machine.c
target/riscv: Remove privilege v1.9 specific CSR related code
2021-05-11 20:01:10 +10:00
meson.build
target/riscv: rvb: generalized reverse
2021-06-08 09:59:45 +10:00
monitor.c
target/riscv: Remove the hardcoded SATP_MODE macro
2021-05-11 20:02:07 +10:00
op_helper.c
target/riscv: Reorg csr instructions
2021-09-01 11:59:12 +10:00
pmp.c
target/riscv: pmp: Fix some typos
2021-07-15 08:56:00 +10:00
pmp.h
target/riscv: Add ePMP CSR access functions
2021-05-11 20:02:06 +10:00
trace-events
target/riscv: Add ePMP CSR access functions
2021-05-11 20:02:06 +10:00
trace.h
…
translate.c
target/riscv: Remove exit_tb and lookup_and_goto_ptr
2021-10-15 16:39:14 -07:00
vector_helper.c
target/riscv: Consolidate RV32/64 32-bit instructions
2021-05-11 20:02:07 +10:00