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e4fdf9df5b
qemu/target/riscv
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Richard Henderson e4fdf9df5b hw/core: Add CPUClass.get_pc 
Populate this new method for all targets.  Always match
the result that would be given by cpu_get_tb_cpu_state,
as we will want these values to correspond in the logs.

Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> (target/sparc)
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
Cc: Eduardo Habkost <eduardo@habkost.net> (supporter:Machine core)
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> (supporter:Machine core)
Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org> (reviewer:Machine core)
Cc: Yanan Wang <wangyanan55@huawei.com> (reviewer:Machine core)
Cc: Michael Rolnik <mrolnik@gmail.com> (maintainer:AVR TCG CPUs)
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> (maintainer:CRIS TCG CPUs)
Cc: Taylor Simpson <tsimpson@quicinc.com> (supporter:Hexagon TCG CPUs)
Cc: Song Gao <gaosong@loongson.cn> (maintainer:LoongArch TCG CPUs)
Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn> (maintainer:LoongArch TCG CPUs)
Cc: Laurent Vivier <laurent@vivier.eu> (maintainer:M68K TCG CPUs)
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> (reviewer:MIPS TCG CPUs)
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> (reviewer:MIPS TCG CPUs)
Cc: Chris Wulff <crwulff@gmail.com> (maintainer:NiosII TCG CPUs)
Cc: Marek Vasut <marex@denx.de> (maintainer:NiosII TCG CPUs)
Cc: Stafford Horne <shorne@gmail.com> (odd fixer:OpenRISC TCG CPUs)
Cc: Yoshinori Sato <ysato@users.sourceforge.jp> (reviewer:RENESAS RX CPUs)
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> (maintainer:SPARC TCG CPUs)
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (maintainer:TriCore TCG CPUs)
Cc: Max Filippov <jcmvbkbc@gmail.com> (maintainer:Xtensa TCG CPUs)
Cc: qemu-arm@nongnu.org (open list:ARM TCG CPUs)
Cc: qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs)
Cc: qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs)
Cc: qemu-s390x@nongnu.org (open list:S390 TCG CPUs)
2022-10-04 12:13:12 -07:00
..
insn_trans target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered 2022-09-27 11:23:57 +10:00
arch_dump.c target-riscv: support QMP dump-guest-memory 2021-03-04 09:43:29 -05:00
bitmanip_helper.c target/riscv: rvk: add support for zbkx extension 2022-04-29 10:47:45 +10:00
common-semi-target.h semihosting: Split out common-semi-target.h 2022-06-28 04:35:07 +05:30
cpu_bits.h target/riscv: debug: Introduce tinfo CSR 2022-09-27 11:23:57 +10:00
cpu_helper.c target/riscv: Honour -semihosting-config userspace=on and enable=on 2022-09-13 17:18:21 +01:00
cpu_user.h Supply missing header guards 2019-06-12 13:20:21 +02:00
cpu-param.h Normalize header guard symbol definition 2022-05-11 16:50:26 +02:00
cpu.c hw/core: Add CPUClass.get_pc 2022-10-04 12:13:12 -07:00
cpu.h target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs 2022-09-27 11:23:57 +10:00
crypto_helper.c target/riscv: rvk: add support for zksed/zksh extension 2022-04-29 10:47:45 +10:00
csr.c target/riscv: debug: Introduce tinfo CSR 2022-09-27 11:23:57 +10:00
debug.c target/riscv: debug: Add initial support of type 6 trigger 2022-09-27 11:23:57 +10:00
debug.h target/riscv: debug: Add initial support of type 6 trigger 2022-09-27 11:23:57 +10:00
fpu_helper.c target/riscv: add support for zhinx/zhinxmin 2022-03-03 13:14:50 +10:00
gdbstub.c target/riscv: Check the correct exception cause in vector GDB stub 2022-09-27 07:04:38 +10:00
helper.h target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered 2022-09-27 11:23:57 +10:00
insn16.decode target/riscv: fix shifts shamt value for rv128c 2022-09-07 09:18:32 +02:00
insn32.decode target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered 2022-09-27 11:23:57 +10:00
instmap.h target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() 2022-09-07 09:18:32 +02:00
internals.h target/riscv: rvv: Add mask agnostic for vv instructions 2022-09-07 09:18:32 +02:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
kvm_riscv.h target/riscv: Support setting external interrupt by KVM 2022-01-21 15:52:56 +10:00
kvm-stub.c target/riscv: Support setting external interrupt by KVM 2022-01-21 15:52:56 +10:00
kvm.c Remove qemu-common.h include from most units 2022-04-06 14:31:55 +02:00
m128_helper.c target/riscv: support for 128-bit M extension 2022-01-08 15:46:10 +10:00
machine.c target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs 2022-09-27 11:23:57 +10:00
meson.build target/riscv: Add stimecmp support 2022-09-07 09:19:15 +02:00
monitor.c target/riscv: Fix incorrect PTE merge in walk_pte 2022-04-29 10:47:46 +10:00
op_helper.c target/riscv: rvk: add CSR support for Zkr 2022-04-29 10:47:45 +10:00
pmp.c target/riscv/pmp: guard against PMP ranges with a negative size 2022-07-03 10:03:20 +10:00
pmp.h target/riscv: rvk: add CSR support for Zkr 2022-04-29 10:47:45 +10:00
pmu.c hw/riscv: virt: Add PMU DT node to the device tree 2022-09-07 09:19:15 +02:00
pmu.h hw/riscv: virt: Add PMU DT node to the device tree 2022-09-07 09:19:15 +02:00
sbi_ecall_interface.h Clean up ill-advised or unusual header guards 2022-05-11 16:50:01 +02:00
time_helper.c target/riscv: Add vstimecmp support 2022-09-07 09:19:15 +02:00
time_helper.h target/riscv: Add stimecmp support 2022-09-07 09:19:15 +02:00
trace-events target/riscv: Add ePMP CSR access functions 2021-05-11 20:02:06 +10:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate.c target/riscv: Honour -semihosting-config userspace=on and enable=on 2022-09-13 17:18:21 +01:00
vector_helper.c target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered 2022-09-27 11:23:57 +10:00
XVentanaCondOps.decode target/riscv: Add XVentanaCondOps custom extension 2022-02-16 12:24:18 +10:00