qemu/target/riscv/insn_trans
Christoph Muellner e05da09b7c
target/riscv: implement Zicbom extension
Zicbom is the Cache-Block Management extension defined in the already
ratified RISC-V Base Cache Management Operation (CBO) ISA extension [1].

The extension contains three instructions: cbo.clean, cbo.flush and
cbo.inval. All of them must be implemented in the same group as LQ and
cbo.zero due to overlapping patterns.

All these instructions can throw a Illegal Instruction/Virtual
Instruction exception, similar to the existing cbo.zero. The same
check_zicbo_envcfg() is used to handle these exceptions.

Aside from that, these instructions also need to handle page faults and
guest page faults. This is done in a new check_zicbom_access() helper.

As with Zicboz, the cache block size for Zicbom is also configurable.
Note that the spec determines that Zicbo[mp] and Zicboz can have
different cache sizes (Section 2.7 of [1]), so we also include a
'cbom_blocksize' to go along with the existing 'cboz_blocksize'. They
are set to the same size, so unless users want to play around with the
settings both sizes will be the same.

[1] https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Signed-off-by: Christoph Muellner <cmuellner@linux.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230224132536.552293-4-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-05 11:49:42 -08:00
..
trans_privileged.c.inc target/riscv: Add itrigger support when icount is not enabled 2023-01-06 10:42:55 +10:00
trans_rva.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_rvb.c.inc target/riscv: fix ctzw behavior 2023-02-07 08:19:23 +10:00
trans_rvd.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_rvf.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_rvh.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_rvi.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_rvk.c.inc target/riscv: rvk: add support for zksed/zksh extension 2022-04-29 10:47:45 +10:00
trans_rvm.c.inc target/riscv: add support for zmmul extension v0.1 2022-06-10 09:31:42 +10:00
trans_rvv.c.inc target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc 2023-03-01 15:17:56 -08:00
trans_rvzawrs.c.inc RISC-V: Add Zawrs ISA extension support 2023-01-06 10:42:55 +10:00
trans_rvzfh.c.inc target/riscv: Simplify the check for Zfhmin and Zhinxmin 2023-03-01 14:57:32 -08:00
trans_rvzicbo.c.inc target/riscv: implement Zicbom extension 2023-03-05 11:49:42 -08:00
trans_rvzicond.c.inc target/riscv: Add support for Zicond extension 2023-03-01 17:07:59 -08:00
trans_svinval.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_xthead.c.inc RISC-V: XTheadMemPair: Remove register restrictions for store-pair 2023-03-01 16:59:50 -08:00
trans_xventanacondops.c.inc target/riscv: Add XVentanaCondOps custom extension 2022-02-16 12:24:18 +10:00