qemu/target
Christoph Muellner e05da09b7c
target/riscv: implement Zicbom extension
Zicbom is the Cache-Block Management extension defined in the already
ratified RISC-V Base Cache Management Operation (CBO) ISA extension [1].

The extension contains three instructions: cbo.clean, cbo.flush and
cbo.inval. All of them must be implemented in the same group as LQ and
cbo.zero due to overlapping patterns.

All these instructions can throw a Illegal Instruction/Virtual
Instruction exception, similar to the existing cbo.zero. The same
check_zicbo_envcfg() is used to handle these exceptions.

Aside from that, these instructions also need to handle page faults and
guest page faults. This is done in a new check_zicbom_access() helper.

As with Zicboz, the cache block size for Zicbom is also configurable.
Note that the spec determines that Zicbo[mp] and Zicboz can have
different cache sizes (Section 2.7 of [1]), so we also include a
'cbom_blocksize' to go along with the existing 'cboz_blocksize'. They
are set to the same size, so unless users want to play around with the
settings both sizes will be the same.

[1] https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Signed-off-by: Christoph Muellner <cmuellner@linux.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20230224132536.552293-4-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-05 11:49:42 -08:00
..
alpha accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
arm Monitor patches for 2023-03-02 2023-03-02 10:54:17 +00:00
avr accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
cris target/cris: Don't use tcg_temp_local_new 2023-03-01 07:33:28 -10:00
hexagon target/hexagon/idef-parser: Drop gen_tmp_local 2023-03-01 07:33:28 -10:00
hppa target/hppa: Don't use tcg_temp_local_new 2023-03-01 07:33:28 -10:00
i386 * bugfixes 2023-03-02 16:13:45 +00:00
loongarch target/loongarch: Implement Chip Configuraiton Version Register(0x0000) 2023-03-03 09:37:30 +08:00
m68k accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
microblaze accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
mips target/mips: Don't use tcg_temp_local_new 2023-03-01 07:33:28 -10:00
nios2 accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
openrisc accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
ppc target/ppc/translate: Add dummy implementation for dcblc instruction 2023-03-03 16:50:17 -03:00
riscv target/riscv: implement Zicbom extension 2023-03-05 11:49:42 -08:00
rx accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
s390x accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
sh4 accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
sparc accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
tricore accel/tcg: Pass max_insn to gen_intermediate_code by pointer 2023-03-01 07:33:27 -10:00
xtensa target/xtensa: Don't use tcg_temp_local_new_* 2023-03-01 07:33:28 -10:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00