1b21fe27e7
A typo in sizeof_reg put the registers at the wrong offset. Simplify the expressions to use positive addresses from the start of uc_mcontext instead of negative addresses from the end of uc_mcontext. Reported-by: Vineet Gupta <vineetg@rivosinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
188 lines
4.8 KiB
ArmAsm
188 lines
4.8 KiB
ArmAsm
/*
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* RISC-V linux replacement vdso.
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*
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* Copyright 2021 Linaro, Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include <asm/unistd.h>
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#include <asm/errno.h>
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#if __riscv_xlen == 32
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# define TARGET_ABI32
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#endif
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#include "vdso-asmoffset.h"
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.text
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.macro endf name
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.globl \name
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.type \name, @function
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.size \name, . - \name
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.endm
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.macro raw_syscall nr
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li a7, \nr
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ecall
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.endm
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.macro vdso_syscall name, nr
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\name:
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raw_syscall \nr
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ret
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endf \name
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.endm
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__vdso_gettimeofday:
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.cfi_startproc
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#ifdef __NR_gettimeofday
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raw_syscall __NR_gettimeofday
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ret
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#else
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/* No gettimeofday, fall back to clock_gettime64. */
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beq a1, zero, 1f
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sw zero, 0(a1) /* tz->tz_minuteswest = 0 */
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sw zero, 4(a1) /* tz->tz_dsttime = 0 */
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1: addi sp, sp, -32
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.cfi_adjust_cfa_offset 32
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sw a0, 16(sp) /* save tv */
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mv a0, sp
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raw_syscall __NR_clock_gettime64
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lw t0, 0(sp) /* timespec.tv_sec.low */
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lw t1, 4(sp) /* timespec.tv_sec.high */
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lw t2, 8(sp) /* timespec.tv_nsec.low */
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lw a1, 16(sp) /* restore tv */
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addi sp, sp, 32
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.cfi_adjust_cfa_offset -32
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bne a0, zero, 9f /* syscall error? */
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li a0, -EOVERFLOW
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bne t1, zero, 9f /* y2038? */
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li a0, 0
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li t3, 1000
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divu t2, t2, t3 /* nsec -> usec */
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sw t0, 0(a1) /* tz->tv_sec */
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sw t2, 4(a1) /* tz->tv_usec */
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9: ret
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#endif
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.cfi_endproc
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endf __vdso_gettimeofday
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.cfi_startproc
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#ifdef __NR_clock_gettime
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vdso_syscall __vdso_clock_gettime, __NR_clock_gettime
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#else
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vdso_syscall __vdso_clock_gettime, __NR_clock_gettime64
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#endif
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#ifdef __NR_clock_getres
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vdso_syscall __vdso_clock_getres, __NR_clock_getres
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#else
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vdso_syscall __vdso_clock_getres, __NR_clock_getres_time64
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#endif
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vdso_syscall __vdso_getcpu, __NR_getcpu
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__vdso_flush_icache:
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/* qemu does not need to flush the icache */
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li a0, 0
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ret
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endf __vdso_flush_icache
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.cfi_endproc
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/*
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* Start the unwind info at least one instruction before the signal
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* trampoline, because the unwinder will assume we are returning
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* after a call site.
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*/
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.cfi_startproc simple
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.cfi_signal_frame
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#define sizeof_reg (__riscv_xlen / 8)
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#define sizeof_freg 8
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#define B_GR 0
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#define B_FR offsetof_freg0
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.cfi_def_cfa 2, offsetof_uc_mcontext
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/* Return address */
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.cfi_return_column 64
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.cfi_offset 64, B_GR + 0 /* pc */
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/* Integer registers */
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.cfi_offset 1, B_GR + 1 * sizeof_reg /* r1 (ra) */
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.cfi_offset 2, B_GR + 2 * sizeof_reg /* r2 (sp) */
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.cfi_offset 3, B_GR + 3 * sizeof_reg
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.cfi_offset 4, B_GR + 4 * sizeof_reg
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.cfi_offset 5, B_GR + 5 * sizeof_reg
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.cfi_offset 6, B_GR + 6 * sizeof_reg
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.cfi_offset 7, B_GR + 7 * sizeof_reg
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.cfi_offset 8, B_GR + 8 * sizeof_reg
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.cfi_offset 9, B_GR + 9 * sizeof_reg
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.cfi_offset 10, B_GR + 10 * sizeof_reg
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.cfi_offset 11, B_GR + 11 * sizeof_reg
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.cfi_offset 12, B_GR + 12 * sizeof_reg
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.cfi_offset 13, B_GR + 13 * sizeof_reg
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.cfi_offset 14, B_GR + 14 * sizeof_reg
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.cfi_offset 15, B_GR + 15 * sizeof_reg
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.cfi_offset 16, B_GR + 16 * sizeof_reg
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.cfi_offset 17, B_GR + 17 * sizeof_reg
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.cfi_offset 18, B_GR + 18 * sizeof_reg
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.cfi_offset 19, B_GR + 19 * sizeof_reg
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.cfi_offset 20, B_GR + 20 * sizeof_reg
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.cfi_offset 21, B_GR + 21 * sizeof_reg
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.cfi_offset 22, B_GR + 22 * sizeof_reg
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.cfi_offset 23, B_GR + 23 * sizeof_reg
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.cfi_offset 24, B_GR + 24 * sizeof_reg
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.cfi_offset 25, B_GR + 25 * sizeof_reg
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.cfi_offset 26, B_GR + 26 * sizeof_reg
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.cfi_offset 27, B_GR + 27 * sizeof_reg
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.cfi_offset 28, B_GR + 28 * sizeof_reg
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.cfi_offset 29, B_GR + 29 * sizeof_reg
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.cfi_offset 30, B_GR + 30 * sizeof_reg
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.cfi_offset 31, B_GR + 31 * sizeof_reg /* r31 */
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.cfi_offset 32, B_FR + 0 /* f0 */
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.cfi_offset 33, B_FR + 1 * sizeof_freg /* f1 */
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.cfi_offset 34, B_FR + 2 * sizeof_freg
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.cfi_offset 35, B_FR + 3 * sizeof_freg
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.cfi_offset 36, B_FR + 4 * sizeof_freg
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.cfi_offset 37, B_FR + 5 * sizeof_freg
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.cfi_offset 38, B_FR + 6 * sizeof_freg
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.cfi_offset 39, B_FR + 7 * sizeof_freg
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.cfi_offset 40, B_FR + 8 * sizeof_freg
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.cfi_offset 41, B_FR + 9 * sizeof_freg
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.cfi_offset 42, B_FR + 10 * sizeof_freg
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.cfi_offset 43, B_FR + 11 * sizeof_freg
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.cfi_offset 44, B_FR + 12 * sizeof_freg
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.cfi_offset 45, B_FR + 13 * sizeof_freg
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.cfi_offset 46, B_FR + 14 * sizeof_freg
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.cfi_offset 47, B_FR + 15 * sizeof_freg
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.cfi_offset 48, B_FR + 16 * sizeof_freg
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.cfi_offset 49, B_FR + 17 * sizeof_freg
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.cfi_offset 50, B_FR + 18 * sizeof_freg
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.cfi_offset 51, B_FR + 19 * sizeof_freg
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.cfi_offset 52, B_FR + 20 * sizeof_freg
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.cfi_offset 53, B_FR + 21 * sizeof_freg
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.cfi_offset 54, B_FR + 22 * sizeof_freg
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.cfi_offset 55, B_FR + 23 * sizeof_freg
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.cfi_offset 56, B_FR + 24 * sizeof_freg
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.cfi_offset 57, B_FR + 25 * sizeof_freg
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.cfi_offset 58, B_FR + 26 * sizeof_freg
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.cfi_offset 59, B_FR + 27 * sizeof_freg
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.cfi_offset 60, B_FR + 28 * sizeof_freg
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.cfi_offset 61, B_FR + 29 * sizeof_freg
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.cfi_offset 62, B_FR + 30 * sizeof_freg
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.cfi_offset 63, B_FR + 31 * sizeof_freg /* f31 */
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nop
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__vdso_rt_sigreturn:
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raw_syscall __NR_rt_sigreturn
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endf __vdso_rt_sigreturn
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.cfi_endproc
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