qemu/target/ppc/translate
Daniel Henrique Barboza 1f26c75191 PPC64/TCG: Implement 'rfebb' instruction
An Event-Based Branch (EBB) allows applications to change the NIA when a
event-based exception occurs. Event-based exceptions are enabled by
setting the Branch Event Status and Control Register (BESCR). If the
event-based exception is enabled when the exception occurs, an EBB
happens.

The following operations happens during an EBB:

- Global Enable (GE) bit of BESCR is set to 0;
- bits 0-61 of the Event-Based Branch Return Register (EBBRR) are set
to the the effective address of the NIA that would have executed if the EBB
didn't happen;
- Instruction fetch and execution will continue in the effective address
contained in the Event-Based Branch Handler Register (EBBHR).

The EBB Handler will process the event and then execute the Return From
Event-Based Branch (rfebb) instruction. rfebb sets BESCR_GE and then
redirects execution to the address pointed in EBBRR. This process is
described in the PowerISA v3.1, Book II, Chapter 6 [1].

This patch implements the rfebb instruction. Descriptions of all
relevant BESCR bits are also added - this patch is only using BESCR_GE,
but the next patches will use the remaining bits.

[1] https://wiki.raptorcs.com/w/images/f/f5/PowerISA_public.v3.1.pdf

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-9-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-12-17 17:57:19 +01:00
..
branch-impl.c.inc PPC64/TCG: Implement 'rfebb' instruction 2021-12-17 17:57:19 +01:00
dfp-impl.c.inc target/ppc: Move ddedpd[q],denbcd[q],dscli[q],dscri[q] to decodetree 2021-11-09 10:32:52 +11:00
fixedpoint-impl.c.inc target/ppc: cntlzdm/cnttzdm implementation without brcond 2021-11-09 10:32:53 +11:00
fp-impl.c.inc target/ppc: Add helper for frsqrtes 2021-12-17 17:57:16 +01:00
fp-ops.c.inc target/ppc: Move load and store floating point instructions to decodetree 2021-11-09 10:32:51 +11:00
spe-impl.c.inc ppc patch queue 2020-08-18 2020-08-24 09:35:21 +01:00
spe-ops.c.inc meson: rename included C source files to .c.inc 2020-08-21 06:18:30 -04:00
vmx-impl.c.inc target/ppc: Implement Vector Mask Move insns 2021-12-17 17:57:13 +01:00
vmx-ops.c.inc target/ppc: Move vinsertb/vinserth/vinsertw/vinsertd to decodetree 2021-11-09 10:32:52 +11:00
vsx-impl.c.inc target/ppc: move xscvqpdp to decodetree 2021-12-17 17:57:18 +01:00
vsx-ops.c.inc target/ppc: move xscvqpdp to decodetree 2021-12-17 17:57:18 +01:00