442c9d682c
Convert the exception-return insns ERET, ERETA and ERETB to decodetree. These were the last insns left in the legacy decoder function disas_uncond_reg_b(), which allows us to remove it. The old decoder explicitly decoded the DRPS instruction, only in order to call unallocated_encoding() on it, exactly as would have happened if it hadn't decoded it. This is because this insn always UNDEFs unless the CPU is in halting-debug state, which we don't emulate. So we list the pattern in a comment in a64.decode, but don't actively decode it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-21-peter.maydell@linaro.org
153 lines
5.8 KiB
Plaintext
153 lines
5.8 KiB
Plaintext
# AArch64 A64 allowed instruction decoding
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#
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# Copyright (c) 2023 Linaro, Ltd
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2.1 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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# This file is processed by scripts/decodetree.py
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#
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&r rn
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&ri rd imm
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&rri_sf rd rn imm sf
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&i imm
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### Data Processing - Immediate
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# PC-rel addressing
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%imm_pcrel 5:s19 29:2
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@pcrel . .. ..... ................... rd:5 &ri imm=%imm_pcrel
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ADR 0 .. 10000 ................... ..... @pcrel
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ADRP 1 .. 10000 ................... ..... @pcrel
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# Add/subtract (immediate)
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%imm12_sh12 10:12 !function=shl_12
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@addsub_imm sf:1 .. ...... . imm:12 rn:5 rd:5
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@addsub_imm12 sf:1 .. ...... . ............ rn:5 rd:5 imm=%imm12_sh12
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ADD_i . 00 100010 0 ............ ..... ..... @addsub_imm
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ADD_i . 00 100010 1 ............ ..... ..... @addsub_imm12
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ADDS_i . 01 100010 0 ............ ..... ..... @addsub_imm
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ADDS_i . 01 100010 1 ............ ..... ..... @addsub_imm12
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SUB_i . 10 100010 0 ............ ..... ..... @addsub_imm
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SUB_i . 10 100010 1 ............ ..... ..... @addsub_imm12
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SUBS_i . 11 100010 0 ............ ..... ..... @addsub_imm
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SUBS_i . 11 100010 1 ............ ..... ..... @addsub_imm12
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# Add/subtract (immediate with tags)
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&rri_tag rd rn uimm6 uimm4
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@addsub_imm_tag . .. ...... . uimm6:6 .. uimm4:4 rn:5 rd:5 &rri_tag
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ADDG_i 1 00 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag
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SUBG_i 1 10 100011 0 ...... 00 .... ..... ..... @addsub_imm_tag
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# Logical (immediate)
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&rri_log rd rn sf dbm
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@logic_imm_64 1 .. ...... dbm:13 rn:5 rd:5 &rri_log sf=1
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@logic_imm_32 0 .. ...... 0 dbm:12 rn:5 rd:5 &rri_log sf=0
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AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_64
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AND_i . 00 100100 . ...... ...... ..... ..... @logic_imm_32
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ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_64
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ORR_i . 01 100100 . ...... ...... ..... ..... @logic_imm_32
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EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_64
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EOR_i . 10 100100 . ...... ...... ..... ..... @logic_imm_32
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ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_64
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ANDS_i . 11 100100 . ...... ...... ..... ..... @logic_imm_32
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# Move wide (immediate)
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&movw rd sf imm hw
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@movw_64 1 .. ...... hw:2 imm:16 rd:5 &movw sf=1
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@movw_32 0 .. ...... 0 hw:1 imm:16 rd:5 &movw sf=0
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MOVN . 00 100101 .. ................ ..... @movw_64
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MOVN . 00 100101 .. ................ ..... @movw_32
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MOVZ . 10 100101 .. ................ ..... @movw_64
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MOVZ . 10 100101 .. ................ ..... @movw_32
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MOVK . 11 100101 .. ................ ..... @movw_64
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MOVK . 11 100101 .. ................ ..... @movw_32
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# Bitfield
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&bitfield rd rn sf immr imms
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@bitfield_64 1 .. ...... 1 immr:6 imms:6 rn:5 rd:5 &bitfield sf=1
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@bitfield_32 0 .. ...... 0 0 immr:5 0 imms:5 rn:5 rd:5 &bitfield sf=0
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SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_64
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SBFM . 00 100110 . ...... ...... ..... ..... @bitfield_32
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BFM . 01 100110 . ...... ...... ..... ..... @bitfield_64
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BFM . 01 100110 . ...... ...... ..... ..... @bitfield_32
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UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_64
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UBFM . 10 100110 . ...... ...... ..... ..... @bitfield_32
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# Extract
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&extract rd rn rm imm sf
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EXTR 1 00 100111 1 0 rm:5 imm:6 rn:5 rd:5 &extract sf=1
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EXTR 0 00 100111 0 0 rm:5 0 imm:5 rn:5 rd:5 &extract sf=0
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# Branches
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%imm26 0:s26 !function=times_4
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@branch . ..... .......................... &i imm=%imm26
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B 0 00101 .......................... @branch
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BL 1 00101 .......................... @branch
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%imm19 5:s19 !function=times_4
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&cbz rt imm sf nz
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CBZ sf:1 011010 nz:1 ................... rt:5 &cbz imm=%imm19
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%imm14 5:s14 !function=times_4
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%imm31_19 31:1 19:5
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&tbz rt imm nz bitpos
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TBZ . 011011 nz:1 ..... .............. rt:5 &tbz imm=%imm14 bitpos=%imm31_19
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B_cond 0101010 0 ................... 0 cond:4 imm=%imm19
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BR 1101011 0000 11111 000000 rn:5 00000 &r
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BLR 1101011 0001 11111 000000 rn:5 00000 &r
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RET 1101011 0010 11111 000000 rn:5 00000 &r
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&braz rn m
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BRAZ 1101011 0000 11111 00001 m:1 rn:5 11111 &braz # BRAAZ, BRABZ
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BLRAZ 1101011 0001 11111 00001 m:1 rn:5 11111 &braz # BLRAAZ, BLRABZ
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&reta m
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RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB
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&bra rn rm m
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BRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB
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BLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB
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ERET 1101011 0100 11111 000000 11111 00000
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ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB
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# We don't need to decode DRPS because it always UNDEFs except when
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# the processor is in halting debug state (which we don't implement).
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# The pattern is listed here as documentation.
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# DRPS 1101011 0101 11111 000000 11111 00000
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