target/arm: Convert ERET, ERETAA, ERETAB to decodetree
Convert the exception-return insns ERET, ERETA and ERETB to decodetree. These were the last insns left in the legacy decoder function disas_uncond_reg_b(), which allows us to remove it. The old decoder explicitly decoded the DRPS instruction, only in order to call unallocated_encoding() on it, exactly as would have happened if it hadn't decoded it. This is because this insn always UNDEFs unless the CPU is in halting-debug state, which we don't emulate. So we list the pattern in a comment in a64.decode, but don't actively decode it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-21-peter.maydell@linaro.org
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@ -142,3 +142,11 @@ RETA 1101011 0010 11111 00001 m:1 11111 11111 &reta # RETAA, RETAB
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&bra rn rm m
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BRA 1101011 1000 11111 00001 m:1 rn:5 rm:5 &bra # BRAA, BRAB
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BLRA 1101011 1001 11111 00001 m:1 rn:5 rm:5 &bra # BLRAA, BLRAB
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ERET 1101011 0100 11111 000000 11111 00000
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ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB
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# We don't need to decode DRPS because it always UNDEFs except when
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# the processor is in halting debug state (which we don't implement).
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# The pattern is listed here as documentation.
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# DRPS 1101011 0101 11111 000000 11111 00000
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@ -1539,6 +1539,61 @@ static bool trans_BLRA(DisasContext *s, arg_bra *a)
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return true;
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}
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static bool trans_ERET(DisasContext *s, arg_ERET *a)
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{
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TCGv_i64 dst;
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if (s->current_el == 0) {
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return false;
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}
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if (s->fgt_eret) {
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gen_exception_insn_el(s, 0, EXCP_UDEF, 0, 2);
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return true;
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}
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dst = tcg_temp_new_i64();
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tcg_gen_ld_i64(dst, cpu_env,
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offsetof(CPUARMState, elr_el[s->current_el]));
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if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
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gen_io_start();
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}
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gen_helper_exception_return(cpu_env, dst);
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/* Must exit loop to check un-masked IRQs */
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s->base.is_jmp = DISAS_EXIT;
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return true;
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}
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static bool trans_ERETA(DisasContext *s, arg_reta *a)
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{
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TCGv_i64 dst;
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if (!dc_isar_feature(aa64_pauth, s)) {
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return false;
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}
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if (s->current_el == 0) {
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return false;
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}
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/* The FGT trap takes precedence over an auth trap. */
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if (s->fgt_eret) {
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gen_exception_insn_el(s, 0, EXCP_UDEF, a->m ? 3 : 2, 2);
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return true;
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}
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dst = tcg_temp_new_i64();
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tcg_gen_ld_i64(dst, cpu_env,
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offsetof(CPUARMState, elr_el[s->current_el]));
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dst = auth_branch_target(s, dst, cpu_X[31], !a->m);
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if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
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gen_io_start();
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}
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gen_helper_exception_return(cpu_env, dst);
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/* Must exit loop to check un-masked IRQs */
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s->base.is_jmp = DISAS_EXIT;
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return true;
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}
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/* HINT instruction group, including various allocated HINTs */
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static void handle_hint(DisasContext *s, uint32_t insn,
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unsigned int op1, unsigned int op2, unsigned int crm)
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@ -2307,111 +2362,6 @@ static void disas_exc(DisasContext *s, uint32_t insn)
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}
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}
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/* Unconditional branch (register)
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* 31 25 24 21 20 16 15 10 9 5 4 0
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* +---------------+-------+-------+-------+------+-------+
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* | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
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* +---------------+-------+-------+-------+------+-------+
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*/
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static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
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{
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unsigned int opc, op2, op3, rn, op4;
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TCGv_i64 dst;
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TCGv_i64 modifier;
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opc = extract32(insn, 21, 4);
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op2 = extract32(insn, 16, 5);
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op3 = extract32(insn, 10, 6);
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rn = extract32(insn, 5, 5);
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op4 = extract32(insn, 0, 5);
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if (op2 != 0x1f) {
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goto do_unallocated;
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}
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switch (opc) {
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case 0:
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case 1:
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case 2:
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case 8:
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case 9:
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/*
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* BR, BLR, RET, RETAA, RETAB, BRAAZ, BRABZ, BLRAAZ, BLRABZ,
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* BRAA, BLRAA: handled in decodetree
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*/
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goto do_unallocated;
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case 4: /* ERET */
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if (s->current_el == 0) {
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goto do_unallocated;
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}
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switch (op3) {
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case 0: /* ERET */
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if (op4 != 0) {
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goto do_unallocated;
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}
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if (s->fgt_eret) {
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gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(op3), 2);
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return;
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}
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dst = tcg_temp_new_i64();
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tcg_gen_ld_i64(dst, cpu_env,
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offsetof(CPUARMState, elr_el[s->current_el]));
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break;
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case 2: /* ERETAA */
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case 3: /* ERETAB */
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if (!dc_isar_feature(aa64_pauth, s)) {
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goto do_unallocated;
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}
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if (rn != 0x1f || op4 != 0x1f) {
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goto do_unallocated;
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}
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/* The FGT trap takes precedence over an auth trap. */
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if (s->fgt_eret) {
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gen_exception_insn_el(s, 0, EXCP_UDEF, syn_erettrap(op3), 2);
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return;
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}
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dst = tcg_temp_new_i64();
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tcg_gen_ld_i64(dst, cpu_env,
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offsetof(CPUARMState, elr_el[s->current_el]));
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if (s->pauth_active) {
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modifier = cpu_X[31];
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if (op3 == 2) {
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gen_helper_autia(dst, cpu_env, dst, modifier);
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} else {
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gen_helper_autib(dst, cpu_env, dst, modifier);
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}
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}
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break;
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default:
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goto do_unallocated;
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}
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if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
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gen_io_start();
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}
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gen_helper_exception_return(cpu_env, dst);
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/* Must exit loop to check un-masked IRQs */
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s->base.is_jmp = DISAS_EXIT;
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return;
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case 5: /* DRPS */
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if (op3 != 0 || op4 != 0 || rn != 0x1f) {
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goto do_unallocated;
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} else {
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unallocated_encoding(s);
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}
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return;
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default:
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do_unallocated:
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unallocated_encoding(s);
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return;
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}
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}
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/* Branches, exception generating and system instructions */
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static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
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{
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@ -2427,9 +2377,6 @@ static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
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disas_exc(s, insn);
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}
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break;
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case 0x6b: /* Unconditional branch (register) */
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disas_uncond_b_reg(s, insn);
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break;
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default:
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unallocated_encoding(s);
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break;
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