qemu/target/ppc/translate
Roman Kapl 50728199c5 target/ppc: add external PID support
External PID is a mechanism present on BookE 2.06 that enables application to
store/load data from different address spaces. There are special version of some
instructions, which operate on alternate address space, which is specified in
the EPLC/EPSC regiser.

This implementation uses two additional MMU modes (mmu_idx) to provide the
address space for the load and store instructions. The QEMU TLB fill code was
modified to recognize these MMU modes and use the values in EPLC/EPSC to find
the proper entry in he PPC TLB. These two QEMU TLBs are also flushed on each
write to EPLC/EPSC.

Following instructions are implemented: dcbfep dcbstep dcbtep dcbtstep dcbzep
dcbzlep icbiep lbepx ldepx lfdepx lhepx lwepx stbepx stdepx stfdepx sthepx
stwepx.

Following vector instructions are not: evlddepx evstddepx lvepx lvepxl stvepx
stvepxl.

Signed-off-by: Roman Kapl <rka@sysgo.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2018-11-08 12:04:40 +11:00
..
dfp-impl.inc.c target/ppc: convert to DisasContextBase 2018-02-16 12:14:39 +11:00
dfp-ops.inc.c
fp-impl.inc.c target/ppc: add external PID support 2018-11-08 12:04:40 +11:00
fp-ops.inc.c target/ppc: add external PID support 2018-11-08 12:04:40 +11:00
spe-impl.inc.c
spe-ops.inc.c
vmx-impl.inc.c ppc: Implement bcdutrunc. instruction 2017-01-31 10:10:14 +11:00
vmx-ops.inc.c ppc: Implement bcdutrunc. instruction 2017-01-31 10:10:14 +11:00
vsx-impl.inc.c target/ppc: optimize various functions using extract op 2017-07-19 14:45:16 -07:00
vsx-ops.inc.c target-ppc: Add xscvqpudz and xscvqpuwz instructions 2017-02-22 11:28:28 +11:00