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target/ppc: optimize various functions using extract op

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Done with the Coccinelle semantic patch
scripts/coccinelle/tcg_gen_extract.cocci.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20170718045540.16322-6-f4bug@amsat.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Philippe Mathieu-Daudé 2017-07-18 01:55:35 -03:00 committed by Richard Henderson
parent 0d9acef240
commit e2622073e0
2 changed files with 15 additions and 30 deletions
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21
target/ppc/translate.c
View File

@ -873,8 +873,7 @@ static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
}
tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
tcg_temp_free(t1);
tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
if (is_isa300(ctx)) {
tcg_gen_mov_tl(cpu_ca32, cpu_ca);
}
@ -1404,8 +1403,7 @@ static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
tcg_temp_free(inv1);
tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
tcg_temp_free(t1);
tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1);
if (is_isa300(ctx)) {
tcg_gen_mov_tl(cpu_ca32, cpu_ca);
}
@ -4336,8 +4334,7 @@ static void gen_mfsrin(DisasContext *ctx)
CHK_SV;
t0 = tcg_temp_new();
tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
tcg_gen_andi_tl(t0, t0, 0xF);
tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
tcg_temp_free(t0);
#endif /* defined(CONFIG_USER_ONLY) */
@ -4368,8 +4365,7 @@ static void gen_mtsrin(DisasContext *ctx)
CHK_SV;
t0 = tcg_temp_new();
tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
tcg_gen_andi_tl(t0, t0, 0xF);
tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
tcg_temp_free(t0);
#endif /* defined(CONFIG_USER_ONLY) */
@ -4403,8 +4399,7 @@ static void gen_mfsrin_64b(DisasContext *ctx)
CHK_SV;
t0 = tcg_temp_new();
tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
tcg_gen_andi_tl(t0, t0, 0xF);
tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
tcg_temp_free(t0);
#endif /* defined(CONFIG_USER_ONLY) */
@ -4435,8 +4430,7 @@ static void gen_mtsrin_64b(DisasContext *ctx)
CHK_SV;
t0 = tcg_temp_new();
tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
tcg_gen_andi_tl(t0, t0, 0xF);
tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4);
gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
tcg_temp_free(t0);
#endif /* defined(CONFIG_USER_ONLY) */
@ -5414,8 +5408,7 @@ static void gen_mfsri(DisasContext *ctx)
CHK_SV;
t0 = tcg_temp_new();
gen_addr_reg_index(ctx, t0);
tcg_gen_shri_tl(t0, t0, 28);
tcg_gen_andi_tl(t0, t0, 0xF);
tcg_gen_extract_tl(t0, t0, 28, 4);
gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
tcg_temp_free(t0);
if (ra != 0 && ra != rd)

24
target/ppc/translate/vsx-impl.inc.c
View File

@ -1248,8 +1248,7 @@ static void gen_xsxexpdp(DisasContext *ctx)
gen_exception(ctx, POWERPC_EXCP_VSXU);
return;
}
tcg_gen_shri_i64(rt, cpu_vsrh(xB(ctx->opcode)), 52);
tcg_gen_andi_i64(rt, rt, 0x7FF);
tcg_gen_extract_i64(rt, cpu_vsrh(xB(ctx->opcode)), 52, 11);
}
static void gen_xsxexpqp(DisasContext *ctx)
@ -1262,8 +1261,7 @@ static void gen_xsxexpqp(DisasContext *ctx)
gen_exception(ctx, POWERPC_EXCP_VSXU);
return;
}
tcg_gen_shri_i64(xth, xbh, 48);
tcg_gen_andi_i64(xth, xth, 0x7FFF);
tcg_gen_extract_i64(xth, xbh, 48, 15);
tcg_gen_movi_i64(xtl, 0);
}
@ -1323,8 +1321,7 @@ static void gen_xsxsigdp(DisasContext *ctx)
zr = tcg_const_i64(0);
nan = tcg_const_i64(2047);
tcg_gen_shri_i64(exp, cpu_vsrh(xB(ctx->opcode)), 52);
tcg_gen_andi_i64(exp, exp, 0x7FF);
tcg_gen_extract_i64(exp, cpu_vsrh(xB(ctx->opcode)), 52, 11);
tcg_gen_movi_i64(t0, 0x0010000000000000);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
@ -1352,8 +1349,7 @@ static void gen_xsxsigqp(DisasContext *ctx)
zr = tcg_const_i64(0);
nan = tcg_const_i64(32767);
tcg_gen_shri_i64(exp, cpu_vsrh(rB(ctx->opcode) + 32), 48);
tcg_gen_andi_i64(exp, exp, 0x7FFF);
tcg_gen_extract_i64(exp, cpu_vsrh(rB(ctx->opcode) + 32), 48, 15);
tcg_gen_movi_i64(t0, 0x0001000000000000);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
@ -1448,10 +1444,8 @@ static void gen_xvxexpdp(DisasContext *ctx)
gen_exception(ctx, POWERPC_EXCP_VSXU);
return;
}
tcg_gen_shri_i64(xth, xbh, 52);
tcg_gen_andi_i64(xth, xth, 0x7FF);
tcg_gen_shri_i64(xtl, xbl, 52);
tcg_gen_andi_i64(xtl, xtl, 0x7FF);
tcg_gen_extract_i64(xth, xbh, 52, 11);
tcg_gen_extract_i64(xtl, xbl, 52, 11);
}
GEN_VSX_HELPER_2(xvxsigsp, 0x00, 0x04, 0, PPC2_ISA300)
@ -1474,16 +1468,14 @@ static void gen_xvxsigdp(DisasContext *ctx)
zr = tcg_const_i64(0);
nan = tcg_const_i64(2047);
tcg_gen_shri_i64(exp, xbh, 52);
tcg_gen_andi_i64(exp, exp, 0x7FF);
tcg_gen_extract_i64(exp, xbh, 52, 11);
tcg_gen_movi_i64(t0, 0x0010000000000000);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
tcg_gen_andi_i64(xth, xbh, 0x000FFFFFFFFFFFFF);
tcg_gen_or_i64(xth, xth, t0);
tcg_gen_shri_i64(exp, xbl, 52);
tcg_gen_andi_i64(exp, exp, 0x7FF);
tcg_gen_extract_i64(exp, xbl, 52, 11);
tcg_gen_movi_i64(t0, 0x0010000000000000);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);