0fc56c4375
The following items in the CPUHexagonState are only used for bookkeeping
within the translation of a packet. With recent changes that eliminate
the need to free TCGv variables, these make more sense to be transient
and kept in DisasContext.
The following items are moved
dczero_addr
branch_taken
this_PC
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-22-tsimpson@quicinc.com>
222 lines
6.8 KiB
C
222 lines
6.8 KiB
C
/*
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* Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HEXAGON_TRANSLATE_H
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#define HEXAGON_TRANSLATE_H
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#include "qemu/bitmap.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "exec/translator.h"
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#include "tcg/tcg-op.h"
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#include "insn.h"
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#include "internal.h"
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typedef struct DisasContext {
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DisasContextBase base;
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Packet *pkt;
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Insn *insn;
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uint32_t next_PC;
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uint32_t mem_idx;
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uint32_t num_packets;
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uint32_t num_insns;
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uint32_t num_hvx_insns;
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int reg_log[REG_WRITES_MAX];
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int reg_log_idx;
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DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS);
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DECLARE_BITMAP(regs_read, TOTAL_PER_THREAD_REGS);
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DECLARE_BITMAP(predicated_regs, TOTAL_PER_THREAD_REGS);
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int preg_log[PRED_WRITES_MAX];
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int preg_log_idx;
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DECLARE_BITMAP(pregs_written, NUM_PREGS);
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DECLARE_BITMAP(pregs_read, NUM_PREGS);
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uint8_t store_width[STORES_MAX];
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bool s1_store_processed;
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int future_vregs_idx;
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int future_vregs_num[VECTOR_TEMPS_MAX];
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int tmp_vregs_idx;
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int tmp_vregs_num[VECTOR_TEMPS_MAX];
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int vreg_log[NUM_VREGS];
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int vreg_log_idx;
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DECLARE_BITMAP(vregs_updated_tmp, NUM_VREGS);
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DECLARE_BITMAP(vregs_updated, NUM_VREGS);
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DECLARE_BITMAP(vregs_select, NUM_VREGS);
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DECLARE_BITMAP(predicated_future_vregs, NUM_VREGS);
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DECLARE_BITMAP(predicated_tmp_vregs, NUM_VREGS);
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DECLARE_BITMAP(vregs_read, NUM_VREGS);
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int qreg_log[NUM_QREGS];
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int qreg_log_idx;
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DECLARE_BITMAP(qregs_read, NUM_QREGS);
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bool pre_commit;
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bool need_commit;
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TCGCond branch_cond;
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target_ulong branch_dest;
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bool is_tight_loop;
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bool short_circuit;
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bool has_hvx_helper;
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TCGv new_value[TOTAL_PER_THREAD_REGS];
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TCGv new_pred_value[NUM_PREGS];
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TCGv pred_written;
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TCGv branch_taken;
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TCGv dczero_addr;
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} DisasContext;
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static inline void ctx_log_pred_write(DisasContext *ctx, int pnum)
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{
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if (!test_bit(pnum, ctx->pregs_written)) {
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ctx->preg_log[ctx->preg_log_idx] = pnum;
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ctx->preg_log_idx++;
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set_bit(pnum, ctx->pregs_written);
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}
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}
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static inline void ctx_log_pred_read(DisasContext *ctx, int pnum)
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{
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set_bit(pnum, ctx->pregs_read);
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}
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static inline void ctx_log_reg_write(DisasContext *ctx, int rnum,
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bool is_predicated)
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{
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if (rnum == HEX_REG_P3_0_ALIASED) {
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for (int i = 0; i < NUM_PREGS; i++) {
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ctx_log_pred_write(ctx, i);
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}
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} else {
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if (!test_bit(rnum, ctx->regs_written)) {
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ctx->reg_log[ctx->reg_log_idx] = rnum;
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ctx->reg_log_idx++;
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set_bit(rnum, ctx->regs_written);
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}
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if (is_predicated) {
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set_bit(rnum, ctx->predicated_regs);
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}
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}
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}
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static inline void ctx_log_reg_write_pair(DisasContext *ctx, int rnum,
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bool is_predicated)
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{
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ctx_log_reg_write(ctx, rnum, is_predicated);
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ctx_log_reg_write(ctx, rnum + 1, is_predicated);
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}
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static inline void ctx_log_reg_read(DisasContext *ctx, int rnum)
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{
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set_bit(rnum, ctx->regs_read);
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}
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static inline void ctx_log_reg_read_pair(DisasContext *ctx, int rnum)
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{
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ctx_log_reg_read(ctx, rnum);
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ctx_log_reg_read(ctx, rnum + 1);
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}
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intptr_t ctx_future_vreg_off(DisasContext *ctx, int regnum,
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int num, bool alloc_ok);
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intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum,
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int num, bool alloc_ok);
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static inline void ctx_log_vreg_write(DisasContext *ctx,
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int rnum, VRegWriteType type,
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bool is_predicated)
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{
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if (type != EXT_TMP) {
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if (!test_bit(rnum, ctx->vregs_updated)) {
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ctx->vreg_log[ctx->vreg_log_idx] = rnum;
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ctx->vreg_log_idx++;
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set_bit(rnum, ctx->vregs_updated);
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}
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set_bit(rnum, ctx->vregs_updated);
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if (is_predicated) {
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set_bit(rnum, ctx->predicated_future_vregs);
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}
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}
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if (type == EXT_NEW) {
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set_bit(rnum, ctx->vregs_select);
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}
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if (type == EXT_TMP) {
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set_bit(rnum, ctx->vregs_updated_tmp);
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if (is_predicated) {
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set_bit(rnum, ctx->predicated_tmp_vregs);
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}
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}
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}
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static inline void ctx_log_vreg_write_pair(DisasContext *ctx,
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int rnum, VRegWriteType type,
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bool is_predicated)
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{
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ctx_log_vreg_write(ctx, rnum ^ 0, type, is_predicated);
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ctx_log_vreg_write(ctx, rnum ^ 1, type, is_predicated);
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}
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static inline void ctx_log_vreg_read(DisasContext *ctx, int rnum)
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{
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set_bit(rnum, ctx->vregs_read);
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}
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static inline void ctx_log_vreg_read_pair(DisasContext *ctx, int rnum)
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{
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ctx_log_vreg_read(ctx, rnum ^ 0);
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ctx_log_vreg_read(ctx, rnum ^ 1);
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}
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static inline void ctx_log_qreg_write(DisasContext *ctx,
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int rnum)
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{
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ctx->qreg_log[ctx->qreg_log_idx] = rnum;
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ctx->qreg_log_idx++;
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}
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static inline void ctx_log_qreg_read(DisasContext *ctx, int qnum)
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{
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set_bit(qnum, ctx->qregs_read);
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}
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extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
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extern TCGv hex_pred[NUM_PREGS];
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extern TCGv hex_slot_cancelled;
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extern TCGv hex_new_value_usr;
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extern TCGv hex_reg_written[TOTAL_PER_THREAD_REGS];
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extern TCGv hex_store_addr[STORES_MAX];
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extern TCGv hex_store_width[STORES_MAX];
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extern TCGv hex_store_val32[STORES_MAX];
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extern TCGv_i64 hex_store_val64[STORES_MAX];
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extern TCGv hex_llsc_addr;
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extern TCGv hex_llsc_val;
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extern TCGv_i64 hex_llsc_val_i64;
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extern TCGv hex_vstore_addr[VSTORES_MAX];
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extern TCGv hex_vstore_size[VSTORES_MAX];
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extern TCGv hex_vstore_pending[VSTORES_MAX];
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bool is_gather_store_insn(DisasContext *ctx);
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void process_store(DisasContext *ctx, int slot_num);
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FIELD(PROBE_PKT_SCALAR_STORE_S0, MMU_IDX, 0, 2)
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FIELD(PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED, 2, 1)
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FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_ST0, 0, 1)
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FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_ST1, 1, 1)
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FIELD(PROBE_PKT_SCALAR_HVX_STORES, HAS_HVX_STORES, 2, 1)
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FIELD(PROBE_PKT_SCALAR_HVX_STORES, S0_IS_PRED, 3, 1)
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FIELD(PROBE_PKT_SCALAR_HVX_STORES, S1_IS_PRED, 4, 1)
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FIELD(PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX, 5, 2)
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#endif
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