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Hexagon (target/hexagon) Move items to DisasContext

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The following items in the CPUHexagonState are only used for bookkeeping
within the translation of a packet.  With recent changes that eliminate
the need to free TCGv variables, these make more sense to be transient
and kept in DisasContext.

The following items are moved
    dczero_addr
    branch_taken
    this_PC

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230427230012.3800327-22-tsimpson@quicinc.com>
This commit is contained in:
Taylor Simpson 2023-04-27 16:00:12 -07:00
parent e5d0d78db4
commit 0fc56c4375
8 changed files with 21 additions and 31 deletions
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2
target/hexagon/README
View File

@ -304,4 +304,4 @@ Here are some handy places to set breakpoints
At the start of execution of a packet for a given PC
br helper_debug_start_packet if env->gpr[41] == 0xdeadbeef
At the end of execution of a packet for a given PC
br helper_debug_commit_end if env->this_PC == 0xdeadbeef
br helper_debug_commit_end if this_PC == 0xdeadbeef

3
target/hexagon/cpu.h
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@ -82,7 +82,6 @@ typedef struct {
typedef struct CPUArchState {
target_ulong gpr[TOTAL_PER_THREAD_REGS];
target_ulong pred[NUM_PREGS];
target_ulong branch_taken;
/* For comparing with LLDB on target - see adjust_stack_ptrs function */
target_ulong last_pc_dumped;
@ -95,11 +94,9 @@ typedef struct CPUArchState {
* Only used when HEX_DEBUG is on, but unconditionally included
* to reduce recompile time when turning HEX_DEBUG on/off.
*/
target_ulong this_PC;
target_ulong reg_written[TOTAL_PER_THREAD_REGS];
MemLog mem_log_stores[STORES_MAX];
target_ulong dczero_addr;
float_status fp_status;

6
target/hexagon/genptr.c
View File

@ -480,9 +480,9 @@ static void gen_write_new_pc_addr(DisasContext *ctx, TCGv addr,
if (ctx->pkt->pkt_has_multi_cof) {
/* If there are multiple branches in a packet, ignore the second one */
tcg_gen_movcond_tl(TCG_COND_NE, hex_gpr[HEX_REG_PC],
hex_branch_taken, tcg_constant_tl(0),
ctx->branch_taken, tcg_constant_tl(0),
hex_gpr[HEX_REG_PC], addr);
tcg_gen_movi_tl(hex_branch_taken, 1);
tcg_gen_movi_tl(ctx->branch_taken, 1);
} else {
tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], addr);
}
@ -503,7 +503,7 @@ static void gen_write_new_pc_pcrel(DisasContext *ctx, int pc_off,
ctx->branch_cond = TCG_COND_ALWAYS;
if (pred != NULL) {
ctx->branch_cond = cond;
tcg_gen_mov_tl(hex_branch_taken, pred);
tcg_gen_mov_tl(ctx->branch_taken, pred);
}
ctx->branch_dest = dest;
}

2
target/hexagon/helper.h
View File

@ -21,7 +21,7 @@
DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_RETURN, noreturn, env, i32)
DEF_HELPER_1(debug_start_packet, void, env)
DEF_HELPER_FLAGS_3(debug_check_store_width, TCG_CALL_NO_WG, void, env, int, int)
DEF_HELPER_FLAGS_4(debug_commit_end, TCG_CALL_NO_WG, void, env, int, int, int)
DEF_HELPER_FLAGS_5(debug_commit_end, TCG_CALL_NO_WG, void, env, i32, int, int, int)
DEF_HELPER_2(commit_store, void, env, int)
DEF_HELPER_3(gather_store, void, env, i32, int)
DEF_HELPER_1(commit_hvx_stores, void, env)

6
target/hexagon/macros.h
View File

@ -648,7 +648,11 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
reg_field_info[FIELD].offset)
#ifdef QEMU_GENERATE
#define fDCZEROA(REG) tcg_gen_mov_tl(hex_dczero_addr, (REG))
#define fDCZEROA(REG) \
do { \
ctx->dczero_addr = tcg_temp_new(); \
tcg_gen_mov_tl(ctx->dczero_addr, (REG)); \
} while (0)
#endif
#define fBRANCH_SPECULATE_STALL(DOTNEWVAL, JUMP_COND, SPEC_DIR, HINTBITNUM, \

5
target/hexagon/op_helper.c
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@ -203,15 +203,14 @@ static void print_store(CPUHexagonState *env, int slot)
}
/* This function is a handy place to set a breakpoint */
void HELPER(debug_commit_end)(CPUHexagonState *env,
void HELPER(debug_commit_end)(CPUHexagonState *env, uint32_t this_PC,
int pred_written, int has_st0, int has_st1)
{
bool reg_printed = false;
bool pred_printed = false;
int i;
HEX_DEBUG_LOG("Packet committed: pc = 0x" TARGET_FMT_lx "\n",
env->this_PC);
HEX_DEBUG_LOG("Packet committed: pc = 0x" TARGET_FMT_lx "\n", this_PC);
HEX_DEBUG_LOG("slot_cancelled = %d\n", env->slot_cancelled);
for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) {

23
target/hexagon/translate.c
View File

@ -41,17 +41,13 @@ static const AnalyzeInsn opcode_analyze[XX_LAST_OPCODE] = {
TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
TCGv hex_pred[NUM_PREGS];
TCGv hex_this_PC;
TCGv hex_slot_cancelled;
TCGv hex_branch_taken;
TCGv hex_new_value_usr;
TCGv hex_reg_written[TOTAL_PER_THREAD_REGS];
TCGv hex_store_addr[STORES_MAX];
TCGv hex_store_width[STORES_MAX];
TCGv hex_store_val32[STORES_MAX];
TCGv_i64 hex_store_val64[STORES_MAX];
TCGv hex_pkt_has_store_s1;
TCGv hex_dczero_addr;
TCGv hex_llsc_addr;
TCGv hex_llsc_val;
TCGv_i64 hex_llsc_val_i64;
@ -157,7 +153,7 @@ static void gen_end_tb(DisasContext *ctx)
if (ctx->branch_cond != TCG_COND_NEVER) {
if (ctx->branch_cond != TCG_COND_ALWAYS) {
TCGLabel *skip = gen_new_label();
tcg_gen_brcondi_tl(ctx->branch_cond, hex_branch_taken, 0, skip);
tcg_gen_brcondi_tl(ctx->branch_cond, ctx->branch_taken, 0, skip);
gen_goto_tb(ctx, 0, ctx->branch_dest, true);
gen_set_label(skip);
gen_goto_tb(ctx, 1, ctx->next_PC, false);
@ -527,16 +523,17 @@ static void gen_start_packet(DisasContext *ctx)
if (HEX_DEBUG) {
/* Handy place to set a breakpoint before the packet executes */
gen_helper_debug_start_packet(cpu_env);
tcg_gen_movi_tl(hex_this_PC, ctx->base.pc_next);
}
/* Initialize the runtime state for packet semantics */
if (need_slot_cancelled(pkt)) {
tcg_gen_movi_tl(hex_slot_cancelled, 0);
}
ctx->branch_taken = NULL;
if (pkt->pkt_has_cof) {
ctx->branch_taken = tcg_temp_new();
if (pkt->pkt_has_multi_cof) {
tcg_gen_movi_tl(hex_branch_taken, 0);
tcg_gen_movi_tl(ctx->branch_taken, 0);
}
if (need_next_PC(ctx)) {
tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], next_PC);
@ -815,7 +812,7 @@ static void process_dczeroa(DisasContext *ctx)
TCGv addr = tcg_temp_new();
TCGv_i64 zero = tcg_constant_i64(0);
tcg_gen_andi_tl(addr, hex_dczero_addr, ~0x1f);
tcg_gen_andi_tl(addr, ctx->dczero_addr, ~0x1f);
tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ);
tcg_gen_addi_tl(addr, addr, 8);
tcg_gen_qemu_st_i64(zero, addr, ctx->mem_idx, MO_UQ);
@ -1002,8 +999,8 @@ static void gen_commit_packet(DisasContext *ctx)
tcg_constant_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa);
/* Handy place to set a breakpoint at the end of execution */
gen_helper_debug_commit_end(cpu_env, ctx->pred_written,
has_st0, has_st1);
gen_helper_debug_commit_end(cpu_env, tcg_constant_tl(ctx->pkt->pc),
ctx->pred_written, has_st0, has_st1);
}
if (pkt->vhist_insn != NULL) {
@ -1196,14 +1193,8 @@ void hexagon_translate_init(void)
offsetof(CPUHexagonState, pred[i]),
hexagon_prednames[i]);
}
hex_this_PC = tcg_global_mem_new(cpu_env,
offsetof(CPUHexagonState, this_PC), "this_PC");
hex_slot_cancelled = tcg_global_mem_new(cpu_env,
offsetof(CPUHexagonState, slot_cancelled), "slot_cancelled");
hex_branch_taken = tcg_global_mem_new(cpu_env,
offsetof(CPUHexagonState, branch_taken), "branch_taken");
hex_dczero_addr = tcg_global_mem_new(cpu_env,
offsetof(CPUHexagonState, dczero_addr), "dczero_addr");
hex_llsc_addr = tcg_global_mem_new(cpu_env,
offsetof(CPUHexagonState, llsc_addr), "llsc_addr");
hex_llsc_val = tcg_global_mem_new(cpu_env,

5
target/hexagon/translate.h
View File

@ -71,6 +71,8 @@ typedef struct DisasContext {
TCGv new_value[TOTAL_PER_THREAD_REGS];
TCGv new_pred_value[NUM_PREGS];
TCGv pred_written;
TCGv branch_taken;
TCGv dczero_addr;
} DisasContext;
static inline void ctx_log_pred_write(DisasContext *ctx, int pnum)
@ -189,16 +191,13 @@ static inline void ctx_log_qreg_read(DisasContext *ctx, int qnum)
extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS];
extern TCGv hex_pred[NUM_PREGS];
extern TCGv hex_this_PC;
extern TCGv hex_slot_cancelled;
extern TCGv hex_branch_taken;
extern TCGv hex_new_value_usr;
extern TCGv hex_reg_written[TOTAL_PER_THREAD_REGS];
extern TCGv hex_store_addr[STORES_MAX];
extern TCGv hex_store_width[STORES_MAX];
extern TCGv hex_store_val32[STORES_MAX];
extern TCGv_i64 hex_store_val64[STORES_MAX];
extern TCGv hex_dczero_addr;
extern TCGv hex_llsc_addr;
extern TCGv hex_llsc_val;
extern TCGv_i64 hex_llsc_val_i64;