qemu/target/arm/tcg
Richard Henderson db36e14501 target/arm: Use PLD, PLDW, PLI not NOP for t32
This fixes a bug in that neither PLI nor PLDW are present in ARMv6T2,
but are introduced with ARMv7 and ARMv7MP respectively.
For clarity, do not use NOP for PLD.

Note that there is no PLDW (literal). Architecturally in the
T1 encoding of "PLD (literal)" bit 5 is "(0)", which means
that it should be zero and if it is not then the behaviour
is CONSTRAINED UNPREDICTABLE (might UNDEF, NOP, or ignore the
value of the bit).

In our implementation we have patterns for both:

+    PLD          1111 1000 -001 1111 1111 ------------        # (literal)
+    PLD          1111 1000 -011 1111 1111 ------------        # (literal)

and so we effectively ignore the value of bit 5.  (This is a
permitted option for this CONSTRAINED UNPREDICTABLE.) This isn't a
behaviour change in this commit, since we previously had NOP lines
for both those patterns.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20240524232121.284515-3-richard.henderson@linaro.org
[PMM: adjusted commit message to note that PLD (lit) T1 bit 5
being 1 is an UNPREDICTABLE case.]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-05-28 14:23:52 +01:00
..
a32-uncond.decode
a32.decode
a64.decode target/arm: Implement ALLINT MSR (immediate) 2024-04-25 10:21:04 +01:00
arm_ldst.h target/arm: Move translate-a32.h, arm_ldst.h, sve_ldst_internal.h to tcg/ 2023-05-12 15:43:36 +01:00
cpu32.c target/arm: Default to 1GHz cntfrq for 'max' and new CPUs 2024-04-30 15:14:15 +01:00
cpu64.c target/arm: Default to 1GHz cntfrq for 'max' and new CPUs 2024-04-30 15:14:15 +01:00
cpu-v7m.c target/arm: Move v7m-related code from cpu32.c into a separate file 2024-03-08 14:45:03 +00:00
crypto_helper.c crypto: Create sm4_subword 2023-09-11 11:45:55 +10:00
helper-a64.c target/arm: Implement ALLINT MSR (immediate) 2024-04-25 10:21:04 +01:00
helper-a64.h target/arm: Implement ALLINT MSR (immediate) 2024-04-25 10:21:04 +01:00
helper-mve.h target/arm: Move helper-{a64,mve,sme,sve}.h to tcg/ 2023-05-12 15:43:37 +01:00
helper-sme.h target/arm: Move helper-{a64,mve,sme,sve}.h to tcg/ 2023-05-12 15:43:37 +01:00
helper-sve.h target/arm: Move helper-{a64,mve,sme,sve}.h to tcg/ 2023-05-12 15:43:37 +01:00
hflags.c target/arm: Restrict translation disabled alignment check to VMSA 2024-04-30 15:01:07 +01:00
iwmmxt_helper.c
m_helper.c exec/cpu: Extract page-protection definitions to page-protection.h 2024-05-06 11:17:15 +02:00
m-nocp.decode
meson.build target/arm: Move v7m-related code from cpu32.c into a separate file 2024-03-08 14:45:03 +00:00
mte_helper.c exec/cpu: Extract page-protection definitions to page-protection.h 2024-05-06 11:17:15 +02:00
mve_helper.c target/arm/tcg: Clean up local variable shadowing 2023-09-29 10:07:14 +02:00
mve.decode
neon_helper.c
neon-dp.decode
neon-ls.decode
neon-shared.decode
op_helper.c target/arm: Allow access to SPSR_hyp from hyp mode 2024-02-15 14:32:38 +00:00
pauth_helper.c target/arm: Move feature test functions to their own header 2023-10-27 11:44:32 +01:00
psci.c target/arm: Expose arm_cpu_mp_affinity() in 'multiprocessing.h' header 2024-01-26 11:30:48 +00:00
sme_helper.c target/arm: Fix 32-bit SMOPA 2024-03-07 12:49:16 +00:00
sme-fa64.decode
sme.decode
sve_helper.c exec/cpu: Extract page-protection definitions to page-protection.h 2024-05-06 11:17:15 +02:00
sve_ldst_internal.h target/arm: Move translate-a32.h, arm_ldst.h, sve_ldst_internal.h to tcg/ 2023-05-12 15:43:36 +01:00
sve.decode target/arm: Demultiplex AESE and AESMC 2023-07-08 07:30:18 +01:00
t16.decode
t32.decode target/arm: Use PLD, PLDW, PLI not NOP for t32 2024-05-28 14:23:52 +01:00
tlb_helper.c target/arm: Split out arm_env_mmu_index 2024-02-03 08:52:25 +10:00
translate-a32.h tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
translate-a64.c accel/tcg: Provide default implementation of disas_log 2024-05-15 08:55:18 +02:00
translate-a64.h target/arm: Split out make_svemte_desc 2024-02-15 11:30:45 +00:00
translate-m-nocp.c tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
translate-mve.c tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
translate-neon.c tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
translate-sme.c target/arm: Split out make_svemte_desc 2024-02-15 11:30:45 +00:00
translate-sve.c target/arm: Handle mte in do_ldrq, do_ldro 2024-02-15 11:30:45 +00:00
translate-vfp.c tcg: Rename cpu_env to tcg_env 2023-10-03 08:01:02 -07:00
translate.c target/arm: Use PLD, PLDW, PLI not NOP for t32 2024-05-28 14:23:52 +01:00
translate.h target/arm: Use insn_start from DisasContextBase 2024-04-09 07:45:09 -10:00
vec_helper.c target/arm: Use clmul_64 2023-09-15 13:57:00 +00:00
vec_internal.h target/arm: Use clmul_16* routines 2023-09-15 13:57:00 +00:00
vfp-uncond.decode
vfp.decode