target/arm: Move v7m-related code from cpu32.c into a separate file
Move the code to a separate file so that we do not have to compile it anymore if CONFIG_ARM_V7M is not set. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-id: 20240308141051.536599-2-thuth@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Thomas Huth
Peter Maydell
parent
fd7f95f23d
commit
bbf6c6dbea
@ -26,6 +26,8 @@ arm_system_ss.add(files(
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'ptw.c',
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))
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arm_user_ss = ss.source_set()
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subdir('hvf')
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if 'CONFIG_TCG' in config_all_accel
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@ -36,3 +38,4 @@ endif
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target_arch += {'arm': arm_ss}
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target_system_arch += {'arm': arm_system_ss}
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target_user_arch += {'arm': arm_user_ss}
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290
target/arm/tcg/cpu-v7m.c
Normal file
290
target/arm/tcg/cpu-v7m.c
Normal file
@ -0,0 +1,290 @@
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/*
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* QEMU ARMv7-M TCG-only CPUs.
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*
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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*
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* This code is licensed under the GNU GPL v2 or later.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "hw/core/tcg-cpu-ops.h"
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#include "internals.h"
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#if !defined(CONFIG_USER_ONLY)
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#include "hw/intc/armv7m_nvic.h"
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static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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CPUClass *cc = CPU_GET_CLASS(cs);
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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bool ret = false;
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/*
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* ARMv7-M interrupt masking works differently than -A or -R.
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* There is no FIQ/IRQ distinction. Instead of I and F bits
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* masking FIQ and IRQ interrupts, an exception is taken only
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* if it is higher priority than the current execution priority
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* (which depends on state like BASEPRI, FAULTMASK and the
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* currently active exception).
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*/
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if (interrupt_request & CPU_INTERRUPT_HARD
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&& (armv7m_nvic_can_take_pending_exception(env->nvic))) {
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cs->exception_index = EXCP_IRQ;
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cc->tcg_ops->do_interrupt(cs);
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ret = true;
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}
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return ret;
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}
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#endif /* !CONFIG_USER_ONLY */
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static void cortex_m0_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V6);
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set_feature(&cpu->env, ARM_FEATURE_M);
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cpu->midr = 0x410cc200;
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/*
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* These ID register values are not guest visible, because
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* we do not implement the Main Extension. They must be set
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* to values corresponding to the Cortex-M0's implemented
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* features, because QEMU generally controls its emulation
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* by looking at ID register fields. We use the same values as
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* for the M3.
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*/
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cpu->isar.id_pfr0 = 0x00000030;
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cpu->isar.id_pfr1 = 0x00000200;
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cpu->isar.id_dfr0 = 0x00100000;
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cpu->id_afr0 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x00000030;
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cpu->isar.id_mmfr1 = 0x00000000;
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cpu->isar.id_mmfr2 = 0x00000000;
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cpu->isar.id_mmfr3 = 0x00000000;
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cpu->isar.id_isar0 = 0x01141110;
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cpu->isar.id_isar1 = 0x02111000;
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cpu->isar.id_isar2 = 0x21112231;
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cpu->isar.id_isar3 = 0x01111110;
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cpu->isar.id_isar4 = 0x01310102;
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cpu->isar.id_isar5 = 0x00000000;
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cpu->isar.id_isar6 = 0x00000000;
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}
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static void cortex_m3_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V7);
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set_feature(&cpu->env, ARM_FEATURE_M);
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set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
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cpu->midr = 0x410fc231;
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cpu->pmsav7_dregion = 8;
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cpu->isar.id_pfr0 = 0x00000030;
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cpu->isar.id_pfr1 = 0x00000200;
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cpu->isar.id_dfr0 = 0x00100000;
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cpu->id_afr0 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x00000030;
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cpu->isar.id_mmfr1 = 0x00000000;
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cpu->isar.id_mmfr2 = 0x00000000;
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cpu->isar.id_mmfr3 = 0x00000000;
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cpu->isar.id_isar0 = 0x01141110;
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cpu->isar.id_isar1 = 0x02111000;
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cpu->isar.id_isar2 = 0x21112231;
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cpu->isar.id_isar3 = 0x01111110;
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cpu->isar.id_isar4 = 0x01310102;
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cpu->isar.id_isar5 = 0x00000000;
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cpu->isar.id_isar6 = 0x00000000;
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}
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static void cortex_m4_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V7);
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set_feature(&cpu->env, ARM_FEATURE_M);
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set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
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set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
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cpu->midr = 0x410fc240; /* r0p0 */
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cpu->pmsav7_dregion = 8;
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cpu->isar.mvfr0 = 0x10110021;
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cpu->isar.mvfr1 = 0x11000011;
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cpu->isar.mvfr2 = 0x00000000;
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cpu->isar.id_pfr0 = 0x00000030;
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cpu->isar.id_pfr1 = 0x00000200;
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cpu->isar.id_dfr0 = 0x00100000;
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cpu->id_afr0 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x00000030;
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cpu->isar.id_mmfr1 = 0x00000000;
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cpu->isar.id_mmfr2 = 0x00000000;
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cpu->isar.id_mmfr3 = 0x00000000;
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cpu->isar.id_isar0 = 0x01141110;
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cpu->isar.id_isar1 = 0x02111000;
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cpu->isar.id_isar2 = 0x21112231;
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cpu->isar.id_isar3 = 0x01111110;
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cpu->isar.id_isar4 = 0x01310102;
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cpu->isar.id_isar5 = 0x00000000;
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cpu->isar.id_isar6 = 0x00000000;
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}
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static void cortex_m7_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V7);
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set_feature(&cpu->env, ARM_FEATURE_M);
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set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
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set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
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cpu->midr = 0x411fc272; /* r1p2 */
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cpu->pmsav7_dregion = 8;
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cpu->isar.mvfr0 = 0x10110221;
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cpu->isar.mvfr1 = 0x12000011;
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cpu->isar.mvfr2 = 0x00000040;
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cpu->isar.id_pfr0 = 0x00000030;
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cpu->isar.id_pfr1 = 0x00000200;
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cpu->isar.id_dfr0 = 0x00100000;
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cpu->id_afr0 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x00100030;
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cpu->isar.id_mmfr1 = 0x00000000;
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cpu->isar.id_mmfr2 = 0x01000000;
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cpu->isar.id_mmfr3 = 0x00000000;
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cpu->isar.id_isar0 = 0x01101110;
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cpu->isar.id_isar1 = 0x02112000;
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cpu->isar.id_isar2 = 0x20232231;
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cpu->isar.id_isar3 = 0x01111131;
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cpu->isar.id_isar4 = 0x01310132;
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cpu->isar.id_isar5 = 0x00000000;
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cpu->isar.id_isar6 = 0x00000000;
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}
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static void cortex_m33_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_M);
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set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
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set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
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set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
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cpu->midr = 0x410fd213; /* r0p3 */
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cpu->pmsav7_dregion = 16;
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cpu->sau_sregion = 8;
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cpu->isar.mvfr0 = 0x10110021;
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cpu->isar.mvfr1 = 0x11000011;
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cpu->isar.mvfr2 = 0x00000040;
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cpu->isar.id_pfr0 = 0x00000030;
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cpu->isar.id_pfr1 = 0x00000210;
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cpu->isar.id_dfr0 = 0x00200000;
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cpu->id_afr0 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x00101F40;
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cpu->isar.id_mmfr1 = 0x00000000;
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cpu->isar.id_mmfr2 = 0x01000000;
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cpu->isar.id_mmfr3 = 0x00000000;
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cpu->isar.id_isar0 = 0x01101110;
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cpu->isar.id_isar1 = 0x02212000;
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cpu->isar.id_isar2 = 0x20232232;
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cpu->isar.id_isar3 = 0x01111131;
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cpu->isar.id_isar4 = 0x01310132;
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cpu->isar.id_isar5 = 0x00000000;
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cpu->isar.id_isar6 = 0x00000000;
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cpu->clidr = 0x00000000;
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cpu->ctr = 0x8000c000;
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}
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static void cortex_m55_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_V8_1M);
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set_feature(&cpu->env, ARM_FEATURE_M);
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set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
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set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
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set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
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cpu->midr = 0x410fd221; /* r0p1 */
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cpu->revidr = 0;
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cpu->pmsav7_dregion = 16;
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cpu->sau_sregion = 8;
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/* These are the MVFR* values for the FPU + full MVE configuration */
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cpu->isar.mvfr0 = 0x10110221;
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cpu->isar.mvfr1 = 0x12100211;
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cpu->isar.mvfr2 = 0x00000040;
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cpu->isar.id_pfr0 = 0x20000030;
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cpu->isar.id_pfr1 = 0x00000230;
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cpu->isar.id_dfr0 = 0x10200000;
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cpu->id_afr0 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x00111040;
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cpu->isar.id_mmfr1 = 0x00000000;
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cpu->isar.id_mmfr2 = 0x01000000;
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cpu->isar.id_mmfr3 = 0x00000011;
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cpu->isar.id_isar0 = 0x01103110;
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cpu->isar.id_isar1 = 0x02212000;
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cpu->isar.id_isar2 = 0x20232232;
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cpu->isar.id_isar3 = 0x01111131;
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cpu->isar.id_isar4 = 0x01310132;
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cpu->isar.id_isar5 = 0x00000000;
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cpu->isar.id_isar6 = 0x00000000;
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cpu->clidr = 0x00000000; /* caches not implemented */
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cpu->ctr = 0x8303c003;
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}
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static const TCGCPUOps arm_v7m_tcg_ops = {
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.initialize = arm_translate_init,
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.synchronize_from_tb = arm_cpu_synchronize_from_tb,
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.debug_excp_handler = arm_debug_excp_handler,
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.restore_state_to_opc = arm_restore_state_to_opc,
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#ifdef CONFIG_USER_ONLY
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.record_sigsegv = arm_cpu_record_sigsegv,
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.record_sigbus = arm_cpu_record_sigbus,
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#else
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.tlb_fill = arm_cpu_tlb_fill,
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.cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
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.do_interrupt = arm_v7m_cpu_do_interrupt,
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.do_transaction_failed = arm_cpu_do_transaction_failed,
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.do_unaligned_access = arm_cpu_do_unaligned_access,
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.adjust_watchpoint_address = arm_adjust_watchpoint_address,
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.debug_check_watchpoint = arm_debug_check_watchpoint,
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.debug_check_breakpoint = arm_debug_check_breakpoint,
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#endif /* !CONFIG_USER_ONLY */
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};
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static void arm_v7m_class_init(ObjectClass *oc, void *data)
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{
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ARMCPUClass *acc = ARM_CPU_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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acc->info = data;
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cc->tcg_ops = &arm_v7m_tcg_ops;
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cc->gdb_core_xml_file = "arm-m-profile.xml";
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}
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static const ARMCPUInfo arm_v7m_cpus[] = {
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{ .name = "cortex-m0", .initfn = cortex_m0_initfn,
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.class_init = arm_v7m_class_init },
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{ .name = "cortex-m3", .initfn = cortex_m3_initfn,
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.class_init = arm_v7m_class_init },
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{ .name = "cortex-m4", .initfn = cortex_m4_initfn,
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.class_init = arm_v7m_class_init },
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{ .name = "cortex-m7", .initfn = cortex_m7_initfn,
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.class_init = arm_v7m_class_init },
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{ .name = "cortex-m33", .initfn = cortex_m33_initfn,
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.class_init = arm_v7m_class_init },
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{ .name = "cortex-m55", .initfn = cortex_m55_initfn,
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.class_init = arm_v7m_class_init },
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};
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static void arm_v7m_cpu_register_types(void)
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{
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size_t i;
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for (i = 0; i < ARRAY_SIZE(arm_v7m_cpus); ++i) {
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arm_cpu_register(&arm_v7m_cpus[i]);
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}
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}
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type_init(arm_v7m_cpu_register_types)
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@ -17,9 +17,6 @@
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#include "hw/boards.h"
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#endif
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#include "cpregs.h"
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#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
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#include "hw/intc/armv7m_nvic.h"
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#endif
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/* Share AArch32 -cpu max features with AArch64. */
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@ -98,32 +95,6 @@ void aa32_max_features(ARMCPU *cpu)
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/* CPU models. These are not needed for the AArch64 linux-user build. */
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#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
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#if !defined(CONFIG_USER_ONLY)
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static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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CPUClass *cc = CPU_GET_CLASS(cs);
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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bool ret = false;
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/*
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* ARMv7-M interrupt masking works differently than -A or -R.
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* There is no FIQ/IRQ distinction. Instead of I and F bits
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* masking FIQ and IRQ interrupts, an exception is taken only
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* if it is higher priority than the current execution priority
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* (which depends on state like BASEPRI, FAULTMASK and the
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* currently active exception).
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*/
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if (interrupt_request & CPU_INTERRUPT_HARD
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&& (armv7m_nvic_can_take_pending_exception(env->nvic))) {
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cs->exception_index = EXCP_IRQ;
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cc->tcg_ops->do_interrupt(cs);
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ret = true;
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}
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return ret;
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}
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#endif /* !CONFIG_USER_ONLY */
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static void arm926_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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@ -571,195 +542,6 @@ static void cortex_a15_initfn(Object *obj)
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define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
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}
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static void cortex_m0_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V6);
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set_feature(&cpu->env, ARM_FEATURE_M);
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cpu->midr = 0x410cc200;
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/*
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* These ID register values are not guest visible, because
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* we do not implement the Main Extension. They must be set
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* to values corresponding to the Cortex-M0's implemented
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* features, because QEMU generally controls its emulation
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* by looking at ID register fields. We use the same values as
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* for the M3.
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*/
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cpu->isar.id_pfr0 = 0x00000030;
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cpu->isar.id_pfr1 = 0x00000200;
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cpu->isar.id_dfr0 = 0x00100000;
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cpu->id_afr0 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x00000030;
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cpu->isar.id_mmfr1 = 0x00000000;
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cpu->isar.id_mmfr2 = 0x00000000;
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cpu->isar.id_mmfr3 = 0x00000000;
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cpu->isar.id_isar0 = 0x01141110;
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cpu->isar.id_isar1 = 0x02111000;
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cpu->isar.id_isar2 = 0x21112231;
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cpu->isar.id_isar3 = 0x01111110;
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cpu->isar.id_isar4 = 0x01310102;
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cpu->isar.id_isar5 = 0x00000000;
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cpu->isar.id_isar6 = 0x00000000;
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}
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static void cortex_m3_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
|
||||
set_feature(&cpu->env, ARM_FEATURE_V7);
|
||||
set_feature(&cpu->env, ARM_FEATURE_M);
|
||||
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
|
||||
cpu->midr = 0x410fc231;
|
||||
cpu->pmsav7_dregion = 8;
|
||||
cpu->isar.id_pfr0 = 0x00000030;
|
||||
cpu->isar.id_pfr1 = 0x00000200;
|
||||
cpu->isar.id_dfr0 = 0x00100000;
|
||||
cpu->id_afr0 = 0x00000000;
|
||||
cpu->isar.id_mmfr0 = 0x00000030;
|
||||
cpu->isar.id_mmfr1 = 0x00000000;
|
||||
cpu->isar.id_mmfr2 = 0x00000000;
|
||||
cpu->isar.id_mmfr3 = 0x00000000;
|
||||
cpu->isar.id_isar0 = 0x01141110;
|
||||
cpu->isar.id_isar1 = 0x02111000;
|
||||
cpu->isar.id_isar2 = 0x21112231;
|
||||
cpu->isar.id_isar3 = 0x01111110;
|
||||
cpu->isar.id_isar4 = 0x01310102;
|
||||
cpu->isar.id_isar5 = 0x00000000;
|
||||
cpu->isar.id_isar6 = 0x00000000;
|
||||
}
|
||||
|
||||
static void cortex_m4_initfn(Object *obj)
|
||||
{
|
||||
ARMCPU *cpu = ARM_CPU(obj);
|
||||
|
||||
set_feature(&cpu->env, ARM_FEATURE_V7);
|
||||
set_feature(&cpu->env, ARM_FEATURE_M);
|
||||
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
|
||||
set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
|
||||
cpu->midr = 0x410fc240; /* r0p0 */
|
||||
cpu->pmsav7_dregion = 8;
|
||||
cpu->isar.mvfr0 = 0x10110021;
|
||||
cpu->isar.mvfr1 = 0x11000011;
|
||||
cpu->isar.mvfr2 = 0x00000000;
|
||||
cpu->isar.id_pfr0 = 0x00000030;
|
||||
cpu->isar.id_pfr1 = 0x00000200;
|
||||
cpu->isar.id_dfr0 = 0x00100000;
|
||||
cpu->id_afr0 = 0x00000000;
|
||||
cpu->isar.id_mmfr0 = 0x00000030;
|
||||
cpu->isar.id_mmfr1 = 0x00000000;
|
||||
cpu->isar.id_mmfr2 = 0x00000000;
|
||||
cpu->isar.id_mmfr3 = 0x00000000;
|
||||
cpu->isar.id_isar0 = 0x01141110;
|
||||
cpu->isar.id_isar1 = 0x02111000;
|
||||
cpu->isar.id_isar2 = 0x21112231;
|
||||
cpu->isar.id_isar3 = 0x01111110;
|
||||
cpu->isar.id_isar4 = 0x01310102;
|
||||
cpu->isar.id_isar5 = 0x00000000;
|
||||
cpu->isar.id_isar6 = 0x00000000;
|
||||
}
|
||||
|
||||
static void cortex_m7_initfn(Object *obj)
|
||||
{
|
||||
ARMCPU *cpu = ARM_CPU(obj);
|
||||
|
||||
set_feature(&cpu->env, ARM_FEATURE_V7);
|
||||
set_feature(&cpu->env, ARM_FEATURE_M);
|
||||
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
|
||||
set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
|
||||
cpu->midr = 0x411fc272; /* r1p2 */
|
||||
cpu->pmsav7_dregion = 8;
|
||||
cpu->isar.mvfr0 = 0x10110221;
|
||||
cpu->isar.mvfr1 = 0x12000011;
|
||||
cpu->isar.mvfr2 = 0x00000040;
|
||||
cpu->isar.id_pfr0 = 0x00000030;
|
||||
cpu->isar.id_pfr1 = 0x00000200;
|
||||
cpu->isar.id_dfr0 = 0x00100000;
|
||||
cpu->id_afr0 = 0x00000000;
|
||||
cpu->isar.id_mmfr0 = 0x00100030;
|
||||
cpu->isar.id_mmfr1 = 0x00000000;
|
||||
cpu->isar.id_mmfr2 = 0x01000000;
|
||||
cpu->isar.id_mmfr3 = 0x00000000;
|
||||
cpu->isar.id_isar0 = 0x01101110;
|
||||
cpu->isar.id_isar1 = 0x02112000;
|
||||
cpu->isar.id_isar2 = 0x20232231;
|
||||
cpu->isar.id_isar3 = 0x01111131;
|
||||
cpu->isar.id_isar4 = 0x01310132;
|
||||
cpu->isar.id_isar5 = 0x00000000;
|
||||
cpu->isar.id_isar6 = 0x00000000;
|
||||
}
|
||||
|
||||
static void cortex_m33_initfn(Object *obj)
|
||||
{
|
||||
ARMCPU *cpu = ARM_CPU(obj);
|
||||
|
||||
set_feature(&cpu->env, ARM_FEATURE_V8);
|
||||
set_feature(&cpu->env, ARM_FEATURE_M);
|
||||
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
|
||||
set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
|
||||
set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
|
||||
cpu->midr = 0x410fd213; /* r0p3 */
|
||||
cpu->pmsav7_dregion = 16;
|
||||
cpu->sau_sregion = 8;
|
||||
cpu->isar.mvfr0 = 0x10110021;
|
||||
cpu->isar.mvfr1 = 0x11000011;
|
||||
cpu->isar.mvfr2 = 0x00000040;
|
||||
cpu->isar.id_pfr0 = 0x00000030;
|
||||
cpu->isar.id_pfr1 = 0x00000210;
|
||||
cpu->isar.id_dfr0 = 0x00200000;
|
||||
cpu->id_afr0 = 0x00000000;
|
||||
cpu->isar.id_mmfr0 = 0x00101F40;
|
||||
cpu->isar.id_mmfr1 = 0x00000000;
|
||||
cpu->isar.id_mmfr2 = 0x01000000;
|
||||
cpu->isar.id_mmfr3 = 0x00000000;
|
||||
cpu->isar.id_isar0 = 0x01101110;
|
||||
cpu->isar.id_isar1 = 0x02212000;
|
||||
cpu->isar.id_isar2 = 0x20232232;
|
||||
cpu->isar.id_isar3 = 0x01111131;
|
||||
cpu->isar.id_isar4 = 0x01310132;
|
||||
cpu->isar.id_isar5 = 0x00000000;
|
||||
cpu->isar.id_isar6 = 0x00000000;
|
||||
cpu->clidr = 0x00000000;
|
||||
cpu->ctr = 0x8000c000;
|
||||
}
|
||||
|
||||
static void cortex_m55_initfn(Object *obj)
|
||||
{
|
||||
ARMCPU *cpu = ARM_CPU(obj);
|
||||
|
||||
set_feature(&cpu->env, ARM_FEATURE_V8);
|
||||
set_feature(&cpu->env, ARM_FEATURE_V8_1M);
|
||||
set_feature(&cpu->env, ARM_FEATURE_M);
|
||||
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
|
||||
set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
|
||||
set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
|
||||
cpu->midr = 0x410fd221; /* r0p1 */
|
||||
cpu->revidr = 0;
|
||||
cpu->pmsav7_dregion = 16;
|
||||
cpu->sau_sregion = 8;
|
||||
/* These are the MVFR* values for the FPU + full MVE configuration */
|
||||
cpu->isar.mvfr0 = 0x10110221;
|
||||
cpu->isar.mvfr1 = 0x12100211;
|
||||
cpu->isar.mvfr2 = 0x00000040;
|
||||
cpu->isar.id_pfr0 = 0x20000030;
|
||||
cpu->isar.id_pfr1 = 0x00000230;
|
||||
cpu->isar.id_dfr0 = 0x10200000;
|
||||
cpu->id_afr0 = 0x00000000;
|
||||
cpu->isar.id_mmfr0 = 0x00111040;
|
||||
cpu->isar.id_mmfr1 = 0x00000000;
|
||||
cpu->isar.id_mmfr2 = 0x01000000;
|
||||
cpu->isar.id_mmfr3 = 0x00000011;
|
||||
cpu->isar.id_isar0 = 0x01103110;
|
||||
cpu->isar.id_isar1 = 0x02212000;
|
||||
cpu->isar.id_isar2 = 0x20232232;
|
||||
cpu->isar.id_isar3 = 0x01111131;
|
||||
cpu->isar.id_isar4 = 0x01310132;
|
||||
cpu->isar.id_isar5 = 0x00000000;
|
||||
cpu->isar.id_isar6 = 0x00000000;
|
||||
cpu->clidr = 0x00000000; /* caches not implemented */
|
||||
cpu->ctr = 0x8303c003;
|
||||
}
|
||||
|
||||
static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
|
||||
/* Dummy the TCM region regs for the moment */
|
||||
{ .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
|
||||
@ -1127,37 +909,6 @@ static void pxa270c5_initfn(Object *obj)
|
||||
cpu->reset_sctlr = 0x00000078;
|
||||
}
|
||||
|
||||
static const TCGCPUOps arm_v7m_tcg_ops = {
|
||||
.initialize = arm_translate_init,
|
||||
.synchronize_from_tb = arm_cpu_synchronize_from_tb,
|
||||
.debug_excp_handler = arm_debug_excp_handler,
|
||||
.restore_state_to_opc = arm_restore_state_to_opc,
|
||||
|
||||
#ifdef CONFIG_USER_ONLY
|
||||
.record_sigsegv = arm_cpu_record_sigsegv,
|
||||
.record_sigbus = arm_cpu_record_sigbus,
|
||||
#else
|
||||
.tlb_fill = arm_cpu_tlb_fill,
|
||||
.cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
|
||||
.do_interrupt = arm_v7m_cpu_do_interrupt,
|
||||
.do_transaction_failed = arm_cpu_do_transaction_failed,
|
||||
.do_unaligned_access = arm_cpu_do_unaligned_access,
|
||||
.adjust_watchpoint_address = arm_adjust_watchpoint_address,
|
||||
.debug_check_watchpoint = arm_debug_check_watchpoint,
|
||||
.debug_check_breakpoint = arm_debug_check_breakpoint,
|
||||
#endif /* !CONFIG_USER_ONLY */
|
||||
};
|
||||
|
||||
static void arm_v7m_class_init(ObjectClass *oc, void *data)
|
||||
{
|
||||
ARMCPUClass *acc = ARM_CPU_CLASS(oc);
|
||||
CPUClass *cc = CPU_CLASS(oc);
|
||||
|
||||
acc->info = data;
|
||||
cc->tcg_ops = &arm_v7m_tcg_ops;
|
||||
cc->gdb_core_xml_file = "arm-m-profile.xml";
|
||||
}
|
||||
|
||||
#ifndef TARGET_AARCH64
|
||||
/*
|
||||
* -cpu max: a CPU with as many features enabled as our emulation supports.
|
||||
@ -1240,18 +991,6 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
|
||||
{ .name = "cortex-a8", .initfn = cortex_a8_initfn },
|
||||
{ .name = "cortex-a9", .initfn = cortex_a9_initfn },
|
||||
{ .name = "cortex-a15", .initfn = cortex_a15_initfn },
|
||||
{ .name = "cortex-m0", .initfn = cortex_m0_initfn,
|
||||
.class_init = arm_v7m_class_init },
|
||||
{ .name = "cortex-m3", .initfn = cortex_m3_initfn,
|
||||
.class_init = arm_v7m_class_init },
|
||||
{ .name = "cortex-m4", .initfn = cortex_m4_initfn,
|
||||
.class_init = arm_v7m_class_init },
|
||||
{ .name = "cortex-m7", .initfn = cortex_m7_initfn,
|
||||
.class_init = arm_v7m_class_init },
|
||||
{ .name = "cortex-m33", .initfn = cortex_m33_initfn,
|
||||
.class_init = arm_v7m_class_init },
|
||||
{ .name = "cortex-m55", .initfn = cortex_m55_initfn,
|
||||
.class_init = arm_v7m_class_init },
|
||||
{ .name = "cortex-r5", .initfn = cortex_r5_initfn },
|
||||
{ .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
|
||||
{ .name = "cortex-r52", .initfn = cortex_r52_initfn },
|
||||
|
||||
@ -55,3 +55,6 @@ arm_ss.add(when: 'TARGET_AARCH64', if_true: files(
|
||||
arm_system_ss.add(files(
|
||||
'psci.c',
|
||||
))
|
||||
|
||||
arm_system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('cpu-v7m.c'))
|
||||
arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files('cpu-v7m.c'))
|
||||
|
||||
Loading…
Reference in New Issue
Block a user