1c687f65b4
We include the files that define PR_MTE_TCF_SHIFT only on Linux, but use them unconditionally. Restrict its use to Linux-only. "It's ugly, but it's not actually wrong." Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
610 lines
17 KiB
C
610 lines
17 KiB
C
/*
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* ARM gdb server stub: AArch64 specific functions.
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*
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* Copyright (c) 2013 SUSE LINUX Products GmbH
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "internals.h"
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#include "gdbstub/helpers.h"
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#include "gdbstub/commands.h"
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#include "tcg/mte_helper.h"
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#if defined(CONFIG_USER_ONLY) && defined(CONFIG_LINUX)
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#include <sys/prctl.h>
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#include "mte_user_helper.h"
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#endif
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int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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if (n < 31) {
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/* Core integer register. */
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return gdb_get_reg64(mem_buf, env->xregs[n]);
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}
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switch (n) {
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case 31:
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return gdb_get_reg64(mem_buf, env->xregs[31]);
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case 32:
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return gdb_get_reg64(mem_buf, env->pc);
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case 33:
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return gdb_get_reg32(mem_buf, pstate_read(env));
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}
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/* Unknown register. */
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return 0;
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}
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int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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uint64_t tmp;
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tmp = ldq_p(mem_buf);
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if (n < 31) {
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/* Core integer register. */
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env->xregs[n] = tmp;
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return 8;
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}
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switch (n) {
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case 31:
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env->xregs[31] = tmp;
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return 8;
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case 32:
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env->pc = tmp;
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return 8;
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case 33:
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/* CPSR */
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pstate_write(env, tmp);
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return 4;
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}
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/* Unknown register. */
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return 0;
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}
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int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray *buf, int reg)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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switch (reg) {
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case 0 ... 31:
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{
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/* 128 bit FP register - quads are in LE order */
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uint64_t *q = aa64_vfp_qreg(env, reg);
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return gdb_get_reg128(buf, q[1], q[0]);
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}
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case 32:
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/* FPSR */
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return gdb_get_reg32(buf, vfp_get_fpsr(env));
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case 33:
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/* FPCR */
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return gdb_get_reg32(buf, vfp_get_fpcr(env));
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default:
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return 0;
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}
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}
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int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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switch (reg) {
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case 0 ... 31:
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/* 128 bit FP register */
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{
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uint64_t *q = aa64_vfp_qreg(env, reg);
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q[0] = ldq_le_p(buf);
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q[1] = ldq_le_p(buf + 8);
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return 16;
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}
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case 32:
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/* FPSR */
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vfp_set_fpsr(env, ldl_p(buf));
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return 4;
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case 33:
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/* FPCR */
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vfp_set_fpcr(env, ldl_p(buf));
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return 4;
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default:
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return 0;
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}
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}
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int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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switch (reg) {
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/* The first 32 registers are the zregs */
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case 0 ... 31:
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{
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int vq, len = 0;
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for (vq = 0; vq < cpu->sve_max_vq; vq++) {
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len += gdb_get_reg128(buf,
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env->vfp.zregs[reg].d[vq * 2 + 1],
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env->vfp.zregs[reg].d[vq * 2]);
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}
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return len;
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}
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case 32:
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return gdb_get_reg32(buf, vfp_get_fpsr(env));
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case 33:
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return gdb_get_reg32(buf, vfp_get_fpcr(env));
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/* then 16 predicates and the ffr */
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case 34 ... 50:
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{
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int preg = reg - 34;
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int vq, len = 0;
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for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
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len += gdb_get_reg64(buf, env->vfp.pregs[preg].p[vq / 4]);
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}
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return len;
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}
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case 51:
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{
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/*
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* We report in Vector Granules (VG) which is 64bit in a Z reg
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* while the ZCR works in Vector Quads (VQ) which is 128bit chunks.
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*/
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int vq = sve_vqm1_for_el(env, arm_current_el(env)) + 1;
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return gdb_get_reg64(buf, vq * 2);
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}
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default:
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/* gdbstub asked for something out our range */
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qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__, reg);
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break;
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}
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return 0;
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}
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int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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/* The first 32 registers are the zregs */
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switch (reg) {
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/* The first 32 registers are the zregs */
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case 0 ... 31:
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{
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int vq, len = 0;
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uint64_t *p = (uint64_t *) buf;
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for (vq = 0; vq < cpu->sve_max_vq; vq++) {
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env->vfp.zregs[reg].d[vq * 2 + 1] = *p++;
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env->vfp.zregs[reg].d[vq * 2] = *p++;
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len += 16;
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}
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return len;
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}
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case 32:
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vfp_set_fpsr(env, *(uint32_t *)buf);
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return 4;
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case 33:
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vfp_set_fpcr(env, *(uint32_t *)buf);
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return 4;
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case 34 ... 50:
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{
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int preg = reg - 34;
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int vq, len = 0;
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uint64_t *p = (uint64_t *) buf;
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for (vq = 0; vq < cpu->sve_max_vq; vq = vq + 4) {
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env->vfp.pregs[preg].p[vq / 4] = *p++;
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len += 8;
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}
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return len;
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}
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case 51:
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/* cannot set vg via gdbstub */
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return 0;
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default:
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/* gdbstub asked for something out our range */
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break;
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}
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return 0;
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}
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int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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switch (reg) {
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case 0: /* pauth_dmask */
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case 1: /* pauth_cmask */
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case 2: /* pauth_dmask_high */
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case 3: /* pauth_cmask_high */
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/*
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* Note that older versions of this feature only contained
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* pauth_{d,c}mask, for use with Linux user processes, and
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* thus exclusively in the low half of the address space.
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*
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* To support system mode, and to debug kernels, two new regs
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* were added to cover the high half of the address space.
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* For the purpose of pauth_ptr_mask, we can use any well-formed
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* address within the address space half -- here, 0 and -1.
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*/
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{
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bool is_data = !(reg & 1);
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bool is_high = reg & 2;
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ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env);
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ARMVAParameters param;
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param = aa64_va_parameters(env, -is_high, mmu_idx, is_data, false);
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return gdb_get_reg64(buf, pauth_ptr_mask(param));
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}
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default:
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return 0;
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}
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}
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int aarch64_gdb_set_pauth_reg(CPUState *cs, uint8_t *buf, int reg)
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{
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/* All pseudo registers are read-only. */
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return 0;
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}
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static void output_vector_union_type(GDBFeatureBuilder *builder, int reg_width,
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const char *name)
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{
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struct TypeSize {
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const char *gdb_type;
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short size;
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char sz, suffix;
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};
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static const struct TypeSize vec_lanes[] = {
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/* quads */
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{ "uint128", 128, 'q', 'u' },
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{ "int128", 128, 'q', 's' },
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/* 64 bit */
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{ "ieee_double", 64, 'd', 'f' },
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{ "uint64", 64, 'd', 'u' },
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{ "int64", 64, 'd', 's' },
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/* 32 bit */
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{ "ieee_single", 32, 's', 'f' },
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{ "uint32", 32, 's', 'u' },
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{ "int32", 32, 's', 's' },
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/* 16 bit */
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{ "ieee_half", 16, 'h', 'f' },
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{ "uint16", 16, 'h', 'u' },
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{ "int16", 16, 'h', 's' },
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/* bytes */
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{ "uint8", 8, 'b', 'u' },
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{ "int8", 8, 'b', 's' },
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};
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static const char suf[] = { 'b', 'h', 's', 'd', 'q' };
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int i, j;
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/* First define types and totals in a whole VL */
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for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
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gdb_feature_builder_append_tag(
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builder, "<vector id=\"%s%c%c\" type=\"%s\" count=\"%d\"/>",
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name, vec_lanes[i].sz, vec_lanes[i].suffix,
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vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size);
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}
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/*
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* Now define a union for each size group containing unsigned and
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* signed and potentially float versions of each size from 128 to
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* 8 bits.
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*/
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for (i = 0; i < ARRAY_SIZE(suf); i++) {
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int bits = 8 << i;
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gdb_feature_builder_append_tag(builder, "<union id=\"%sn%c\">",
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name, suf[i]);
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for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {
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if (vec_lanes[j].size == bits) {
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gdb_feature_builder_append_tag(
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builder, "<field name=\"%c\" type=\"%s%c%c\"/>",
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vec_lanes[j].suffix, name,
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vec_lanes[j].sz, vec_lanes[j].suffix);
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}
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}
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gdb_feature_builder_append_tag(builder, "</union>");
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}
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/* And now the final union of unions */
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gdb_feature_builder_append_tag(builder, "<union id=\"%s\">", name);
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for (i = ARRAY_SIZE(suf) - 1; i >= 0; i--) {
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gdb_feature_builder_append_tag(builder,
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"<field name=\"%c\" type=\"%sn%c\"/>",
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suf[i], name, suf[i]);
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}
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gdb_feature_builder_append_tag(builder, "</union>");
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}
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GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cs, int base_reg)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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int reg_width = cpu->sve_max_vq * 128;
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int pred_width = cpu->sve_max_vq * 16;
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GDBFeatureBuilder builder;
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char *name;
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int reg = 0;
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int i;
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gdb_feature_builder_init(&builder, &cpu->dyn_svereg_feature.desc,
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"org.gnu.gdb.aarch64.sve", "sve-registers.xml",
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base_reg);
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/* Create the vector union type. */
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output_vector_union_type(&builder, reg_width, "svev");
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/* Create the predicate vector type. */
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gdb_feature_builder_append_tag(
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&builder, "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",
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pred_width / 8);
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/* Define the vector registers. */
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for (i = 0; i < 32; i++) {
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name = g_strdup_printf("z%d", i);
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gdb_feature_builder_append_reg(&builder, name, reg_width, reg++,
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"svev", NULL);
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}
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/* fpscr & status registers */
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gdb_feature_builder_append_reg(&builder, "fpsr", 32, reg++,
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"int", "float");
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gdb_feature_builder_append_reg(&builder, "fpcr", 32, reg++,
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"int", "float");
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/* Define the predicate registers. */
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for (i = 0; i < 16; i++) {
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name = g_strdup_printf("p%d", i);
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gdb_feature_builder_append_reg(&builder, name, pred_width, reg++,
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"svep", NULL);
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}
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gdb_feature_builder_append_reg(&builder, "ffr", pred_width, reg++,
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"svep", "vector");
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/* Define the vector length pseudo-register. */
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gdb_feature_builder_append_reg(&builder, "vg", 64, reg++, "int", NULL);
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gdb_feature_builder_end(&builder);
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return &cpu->dyn_svereg_feature.desc;
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}
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#ifdef CONFIG_USER_ONLY
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int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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uint64_t tcf0;
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assert(reg == 0);
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tcf0 = extract64(env->cp15.sctlr_el[1], 38, 2);
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return gdb_get_reg64(buf, tcf0);
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}
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int aarch64_gdb_set_tag_ctl_reg(CPUState *cs, uint8_t *buf, int reg)
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{
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#if defined(CONFIG_LINUX)
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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uint8_t tcf;
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assert(reg == 0);
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tcf = *buf << PR_MTE_TCF_SHIFT;
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if (!tcf) {
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return 0;
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}
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/*
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* 'tag_ctl' register is actually a "pseudo-register" provided by GDB to
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* expose options regarding the type of MTE fault that can be controlled at
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* runtime.
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*/
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arm_set_mte_tcf0(env, tcf);
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return 1;
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#else
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return 0;
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#endif
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}
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static void handle_q_memtag(GArray *params, void *user_ctx)
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{
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ARMCPU *cpu = ARM_CPU(user_ctx);
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CPUARMState *env = &cpu->env;
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uint64_t addr = gdb_get_cmd_param(params, 0)->val_ull;
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uint64_t len = gdb_get_cmd_param(params, 1)->val_ul;
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int type = gdb_get_cmd_param(params, 2)->val_ul;
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uint8_t *tags;
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uint8_t addr_tag;
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g_autoptr(GString) str_buf = g_string_new(NULL);
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/*
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* GDB does not query multiple tags for a memory range on remote targets, so
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* that's not supported either by gdbstub.
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*/
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if (len != 1) {
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gdb_put_packet("E02");
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}
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/* GDB never queries a tag different from an allocation tag (type 1). */
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if (type != 1) {
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gdb_put_packet("E03");
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}
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/* Note that tags are packed here (2 tags packed in one byte). */
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tags = allocation_tag_mem_probe(env, 0, addr, MMU_DATA_LOAD, 8 /* 64-bit */,
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MMU_DATA_LOAD, true, 0);
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if (!tags) {
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/* Address is not in a tagged region. */
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gdb_put_packet("E04");
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return;
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}
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/* Unpack tag from byte. */
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addr_tag = load_tag1(addr, tags);
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g_string_printf(str_buf, "m%.2x", addr_tag);
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gdb_put_packet(str_buf->str);
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}
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static void handle_q_isaddresstagged(GArray *params, void *user_ctx)
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{
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ARMCPU *cpu = ARM_CPU(user_ctx);
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CPUARMState *env = &cpu->env;
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uint64_t addr = gdb_get_cmd_param(params, 0)->val_ull;
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uint8_t *tags;
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const char *reply;
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tags = allocation_tag_mem_probe(env, 0, addr, MMU_DATA_LOAD, 8 /* 64-bit */,
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MMU_DATA_LOAD, true, 0);
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reply = tags ? "01" : "00";
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gdb_put_packet(reply);
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}
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static void handle_Q_memtag(GArray *params, void *user_ctx)
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{
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ARMCPU *cpu = ARM_CPU(user_ctx);
|
|
CPUARMState *env = &cpu->env;
|
|
|
|
uint64_t start_addr = gdb_get_cmd_param(params, 0)->val_ull;
|
|
uint64_t len = gdb_get_cmd_param(params, 1)->val_ul;
|
|
int type = gdb_get_cmd_param(params, 2)->val_ul;
|
|
char const *new_tags_str = gdb_get_cmd_param(params, 3)->data;
|
|
|
|
uint64_t end_addr;
|
|
|
|
int num_new_tags;
|
|
uint8_t *tags;
|
|
|
|
g_autoptr(GByteArray) new_tags = g_byte_array_new();
|
|
|
|
/*
|
|
* Only the allocation tag (i.e. type 1) can be set at the stub side.
|
|
*/
|
|
if (type != 1) {
|
|
gdb_put_packet("E02");
|
|
return;
|
|
}
|
|
|
|
end_addr = start_addr + (len - 1); /* 'len' is always >= 1 */
|
|
/* Check if request's memory range does not cross page boundaries. */
|
|
if ((start_addr ^ end_addr) & TARGET_PAGE_MASK) {
|
|
gdb_put_packet("E03");
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Get all tags in the page starting from the tag of the start address.
|
|
* Note that there are two tags packed into a single byte here.
|
|
*/
|
|
tags = allocation_tag_mem_probe(env, 0, start_addr, MMU_DATA_STORE,
|
|
8 /* 64-bit */, MMU_DATA_STORE, true, 0);
|
|
if (!tags) {
|
|
/* Address is not in a tagged region. */
|
|
gdb_put_packet("E04");
|
|
return;
|
|
}
|
|
|
|
/* Convert tags provided by GDB, 2 hex digits per tag. */
|
|
num_new_tags = strlen(new_tags_str) / 2;
|
|
gdb_hextomem(new_tags, new_tags_str, num_new_tags);
|
|
|
|
uint64_t address = start_addr;
|
|
int new_tag_index = 0;
|
|
while (address <= end_addr) {
|
|
uint8_t new_tag;
|
|
int packed_index;
|
|
|
|
/*
|
|
* Find packed tag index from unpacked tag index. There are two tags
|
|
* in one packed index (one tag per nibble).
|
|
*/
|
|
packed_index = new_tag_index / 2;
|
|
|
|
new_tag = new_tags->data[new_tag_index % num_new_tags];
|
|
store_tag1(address, tags + packed_index, new_tag);
|
|
|
|
address += TAG_GRANULE;
|
|
new_tag_index++;
|
|
}
|
|
|
|
gdb_put_packet("OK");
|
|
}
|
|
|
|
enum Command {
|
|
qMemTags,
|
|
qIsAddressTagged,
|
|
QMemTags,
|
|
NUM_CMDS
|
|
};
|
|
|
|
static const GdbCmdParseEntry cmd_handler_table[NUM_CMDS] = {
|
|
[qMemTags] = {
|
|
.handler = handle_q_memtag,
|
|
.cmd_startswith = true,
|
|
.cmd = "MemTags:",
|
|
.schema = "L,l:l0",
|
|
.need_cpu_context = true
|
|
},
|
|
[qIsAddressTagged] = {
|
|
.handler = handle_q_isaddresstagged,
|
|
.cmd_startswith = true,
|
|
.cmd = "IsAddressTagged:",
|
|
.schema = "L0",
|
|
.need_cpu_context = true
|
|
},
|
|
[QMemTags] = {
|
|
.handler = handle_Q_memtag,
|
|
.cmd_startswith = true,
|
|
.cmd = "MemTags:",
|
|
.schema = "L,l:l:s0",
|
|
.need_cpu_context = true
|
|
},
|
|
};
|
|
#endif /* CONFIG_USER_ONLY */
|
|
|
|
void aarch64_cpu_register_gdb_commands(ARMCPU *cpu, GString *qsupported,
|
|
GPtrArray *qtable, GPtrArray *stable)
|
|
{
|
|
#ifdef CONFIG_USER_ONLY
|
|
/* MTE */
|
|
if (cpu_isar_feature(aa64_mte, cpu)) {
|
|
g_string_append(qsupported, ";memory-tagging+");
|
|
|
|
g_ptr_array_add(qtable, (gpointer) &cmd_handler_table[qMemTags]);
|
|
g_ptr_array_add(qtable, (gpointer) &cmd_handler_table[qIsAddressTagged]);
|
|
g_ptr_array_add(stable, (gpointer) &cmd_handler_table[QMemTags]);
|
|
}
|
|
#endif
|
|
}
|