Richard Henderson d9996d0904 target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index ...

Use the target-specific function name in preference
to the generic name.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

2024-02-03 16:46:10 +10:00

..

insn_trans

target/riscv: Add support for Zacas extension

2024-01-10 18:47:47 +10:00

kvm

target/riscv/kvm: add RVV and Vector CSR regs

2024-01-10 18:47:47 +10:00

tcg

include/qemu: Add TCGCPUOps typedef to typedefs.h

2024-01-29 21:04:10 +10:00

arch_dump.c

…

bitmanip_helper.c

…

common-semi-target.h

…

cpu_bits.h

target/riscv: Add M-mode virtual interrupt and IRQ filtering support.

2023-11-07 11:02:17 +10:00

cpu_cfg.h

target/riscv: implement svade

2024-01-10 18:47:47 +10:00

cpu_helper.c

target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index

2024-02-03 16:46:10 +10:00

cpu_user.h

…

cpu_vendorid.h

…

cpu-param.h

…

cpu-qom.h

target/riscv: add rva22s64 cpu

2024-01-10 18:47:47 +10:00

cpu.c

target/riscv: Ensure mideleg is set correctly on reset

2024-01-10 18:47:47 +10:00

cpu.h

target/riscv: Rename riscv_cpu_mmu_index to riscv_env_mmu_index

2024-02-03 16:46:10 +10:00

crypto_helper.c

…

csr.c

target/riscv: Assert that the CSR numbers will be correct

2024-01-10 18:47:47 +10:00

debug.c

…

debug.h

…

fpu_helper.c

…

gdbstub.c

target/riscv: rename ext_icsr to ext_zicsr

2023-11-07 11:02:17 +10:00

helper.h

…

insn16.decode

…

insn32.decode

target/riscv: Add support for Zacas extension

2024-01-10 18:47:47 +10:00

instmap.h

…

internals.h

target/riscv: Use env_archcpu() in [check_]nanbox()

2023-11-07 12:13:27 +01:00

Kconfig

…

m128_helper.c

…

machine.c

target/riscv: Constify VMState in machine.c

2023-12-29 11:17:30 +11:00

meson.build

target/riscv: move KVM only files to kvm subdir

2023-10-12 12:20:24 +10:00

monitor.c

…

op_helper.c

target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index

2024-02-03 16:46:10 +10:00

pmp.c

target/riscv: pmp: Ignore writes when RW=01 and MML=0

2024-01-10 18:47:47 +10:00

pmp.h

target/riscv/pmp: Use hwaddr instead of target_ulong for RV32

2024-01-10 18:47:46 +10:00

pmu.c

target/riscv: Add "pmu-mask" property to replace "pmu-num"

2023-11-07 11:06:02 +10:00

pmu.h

target/riscv: Use existing PMU counter mask in FDT generation

2023-11-07 11:06:02 +10:00

riscv-qmp-cmds.c

riscv-qmp-cmds.c: add profile flags in cpu-model-expansion

2024-01-10 18:47:47 +10:00

sbi_ecall_interface.h

…

time_helper.c

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time_helper.h

…

trace-events

…

trace.h

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translate.c

target: Use vaddr in gen_intermediate_code

2024-01-29 07:06:03 +10:00

vcrypto_helper.c

…

vector_helper.c

target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index

2024-02-03 16:46:10 +10:00

vector_internals.c

riscv: Clean up includes

2024-01-30 21:20:20 +03:00

vector_internals.h

riscv: Clean up includes

2024-01-30 21:20:20 +03:00

xthead.decode

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XVentanaCondOps.decode

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zce_helper.c

…