Zong Li 8ba26b0b2b target/riscv: Fix the range of pmpcfg of CSR funcion table ...

The range of Physical Memory Protection should be from CSR_PMPCFG0
to CSR_PMPCFG3, not to CSR_PMPADDR9.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <eae49e9252c9596e4f3bdb471772f79235141a87.1595335112.git.zong.li@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2020-07-22 09:41:36 -07:00

..

insn_trans

target/riscv: fix vector index load/store constraints

2020-07-22 09:39:46 -07:00

cpu_bits.h

target/riscv: support vector extension csr

2020-07-02 09:19:32 -07:00

cpu_helper.c

…

cpu_user.h

…

cpu-param.h

…

cpu.c

target/riscv: configure and turn on vector extension from command line

2020-07-02 09:19:34 -07:00

cpu.h

target/riscv: fix vill bit index in vtype register

2020-07-13 17:25:37 -07:00

csr.c

target/riscv: Fix the range of pmpcfg of CSR funcion table

2020-07-22 09:41:36 -07:00

fpu_helper.c

target/riscv: vector floating-point classify instructions

2020-07-02 09:19:33 -07:00

gdbstub.c

…

helper.h

target/riscv: vector compress instruction

2020-07-02 09:19:34 -07:00

insn16-32.decode

…

insn16-64.decode

…

insn16.decode

…

insn32-64.decode

target/riscv: add vector amo operations

2020-07-02 09:19:33 -07:00

insn32.decode

target/riscv: vector compress instruction

2020-07-02 09:19:34 -07:00

instmap.h

…

internals.h

target/riscv: integer scalar move instruction

2020-07-02 09:19:33 -07:00

Makefile.objs

target/riscv: add vector configure instruction

2020-07-02 09:19:32 -07:00

monitor.c

…

op_helper.c

…

pmp.c

target/riscv: Fix pmp NA4 implementation

2020-07-13 17:25:37 -07:00

pmp.h

…

trace-events

…

translate.c

target/riscv: add vector stride load and store instructions

2020-07-02 09:19:32 -07:00

vector_helper.c

target/riscv: vector compress instruction

2020-07-02 09:19:34 -07:00