target/riscv: fix vector index load/store constraints
Although not explicitly specified that the the destination vector register groups cannot overlap the source vector register group, it is still necessary. And this constraint has been added to the v0.8 spec. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200721133742.2298-2-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -513,13 +513,21 @@ static bool ld_index_op(DisasContext *s, arg_rnfvm *a, uint8_t seq)
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return ldst_index_trans(a->rd, a->rs1, a->rs2, data, fn, s);
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}
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/*
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* For vector indexed segment loads, the destination vector register
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* groups cannot overlap the source vector register group (specified by
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* `vs2`), else an illegal instruction exception is raised.
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*/
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static bool ld_index_check(DisasContext *s, arg_rnfvm* a)
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{
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return (vext_check_isa_ill(s) &&
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vext_check_overlap_mask(s, a->rd, a->vm, false) &&
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vext_check_reg(s, a->rd, false) &&
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vext_check_reg(s, a->rs2, false) &&
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vext_check_nf(s, a->nf));
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vext_check_nf(s, a->nf) &&
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((a->nf == 1) ||
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vext_check_overlap_group(a->rd, a->nf << s->lmul,
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a->rs2, 1 << s->lmul)));
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}
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GEN_VEXT_TRANS(vlxb_v, 0, rnfvm, ld_index_op, ld_index_check)
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