qemu/target/loongarch/insn_trans
Richard Henderson 10dcb08b03 target/loongarch: Remove cpu_fcsr0
All of the fpu operations are defined with TCG_CALL_NO_WG, but they
all modify FCSR0.  The most efficient way to fix this is to remove
cpu_fcsr0, and instead use explicit load and store operations for the
two instructions that manipulate that value.

Acked-by: Qi Hu <huqi@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
Reported-by: Feiyang Chen <chenfeiyang@loongson.cn>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-08-08 19:42:53 -07:00
..
trans_arith.c.inc
trans_atomic.c.inc target/loongarch: Add fixed point atomic instruction translation 2022-06-06 18:09:03 +00:00
trans_bit.c.inc target/loongarch: Add fixed point bit instruction translation 2022-06-06 18:09:03 +00:00
trans_branch.c.inc target/loongarch: Add branch instruction translation 2022-06-06 18:09:03 +00:00
trans_extra.c.inc target/loongarch: Add timer related instructions support. 2022-06-06 18:09:03 +00:00
trans_farith.c.inc target/loongarch: Add floating point arithmetic instruction translation 2022-06-06 18:09:03 +00:00
trans_fcmp.c.inc target/loongarch: Add floating point comparison instruction translation 2022-06-06 18:09:03 +00:00
trans_fcnv.c.inc target/loongarch: Add floating point conversion instruction translation 2022-06-06 18:09:03 +00:00
trans_fmemory.c.inc target/loongarch: Add floating point load/store instruction translation 2022-06-06 18:09:03 +00:00
trans_fmov.c.inc target/loongarch: Remove cpu_fcsr0 2022-08-08 19:42:53 -07:00
trans_memory.c.inc target/loongarch: Add fixed point atomic instruction translation 2022-06-06 18:09:03 +00:00
trans_privileged.c.inc target/loongarch: Adjust functions and structure to support user-mode 2022-07-04 11:08:58 +05:30
trans_shift.c.inc target/loongarch: Add fixed point shift instruction translation 2022-06-06 18:09:03 +00:00