Bin Meng cfeb8a17c8 hw/riscv: virt: Limit RAM size in a 32-bit system ... RV32 supports 34-bit physical address hence the maximum RAM size should be limited. Limit the RAM size to 10 GiB, which leaves some room for PCIe high mmio space. For 32-bit host, this is not needed as machine->ram_size cannot represent a RAM size that big. Use a #if size test to only do the size limitation for the 64-bit host. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210220144807.819-4-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-03-04 09:43:29 -05:00
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boot.c	riscv: Pass RISCVHartArrayState by pointer	2021-01-16 14:34:46 -08:00
Kconfig	hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card	2021-03-04 09:43:29 -05:00
meson.build	hw/riscv: Always build riscv_hart.c	2020-09-09 15:54:19 -07:00
microchip_pfsoc.c	hw/riscv: Drop 'struct MemmapEntry'	2021-03-04 09:43:29 -05:00
numa.c	hw/riscv: Add helpers for RISC-V multi-socket NUMA machines	2020-08-25 09:11:35 -07:00
opentitan.c	hw/riscv: Drop 'struct MemmapEntry'	2021-03-04 09:43:29 -05:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
sifive_e.c	hw/riscv: Drop 'struct MemmapEntry'	2021-03-04 09:43:29 -05:00
sifive_u.c	hw/riscv: Drop 'struct MemmapEntry'	2021-03-04 09:43:29 -05:00
spike.c	hw/riscv: Drop 'struct MemmapEntry'	2021-03-04 09:43:29 -05:00
virt.c	hw/riscv: virt: Limit RAM size in a 32-bit system	2021-03-04 09:43:29 -05:00