Rob Herring ce8f0905a5 pl011: fix UARTRSR accesses corrupting the UARTCR value
Offset 4 is UARTRSR/UARTECR, not the UARTCR. The UARTCR would be
corrupted if the UARTRSR is ever written. Fix by implementing a correct
model of the UARTRSR/UARTECR register. Reads of this register simply
reflect the error bits in data register. Only breaks can be triggered in
QEMU. With the pl011_can_receive function, we effectively have flow
control between the host and the model. Framing and parity errors simply
don't make sense in the model and will never occur.

Signed-off-by: Rob Herring <rob.herring@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1395166721-15716-3-git-send-email-robherring2@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-03-18 19:38:55 +00:00
2014-03-12 16:45:25 +00:00
2014-03-13 20:15:37 +01:00
2014-03-03 09:46:27 +04:00
2014-03-13 20:15:37 +01:00
2014-03-15 13:54:18 +04:00
2014-03-15 18:22:11 +00:00
2014-03-13 15:33:04 +00:00
2014-03-12 17:26:32 +01:00
2014-03-13 14:42:24 +01:00
2014-03-17 11:50:19 +00:00
2014-03-13 14:42:24 +01:00
2014-02-21 21:02:23 +01:00
2014-03-13 14:34:16 +00:00
2014-02-25 14:30:28 +01:00
2014-03-17 13:21:11 +01:00
2014-03-05 03:06:24 +01:00
2014-02-17 11:57:23 -05:00
2014-03-13 20:08:15 -07:00
2014-03-17 15:51:57 +00:00

Read the documentation in qemu-doc.html or on http://wiki.qemu-project.org

- QEMU team
Description
No description provided
Readme 404 MiB
Languages
C 82.6%
C++ 6.5%
Python 3.4%
Dylan 2.9%
Shell 1.6%
Other 2.8%