Alex Bennée c65d7080d8 hw/riscv: migrate fdt field to generic MachineState ... This is a mechanical change to make the fdt available through MachineState. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210303173642.3805-3-alex.bennee@linaro.org>		2021-03-10 15:34:11 +00:00
..
boot_opensbi.h
boot.h	riscv: Pass RISCVHartArrayState by pointer	2021-01-16 14:34:46 -08:00
microchip_pfsoc.h
numa.h
opentitan.h	riscv/opentitan: Update the OpenTitan memory layout	2020-12-17 21:56:44 -08:00
riscv_hart.h
sifive_cpu.h
sifive_e.h
sifive_u.h	hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value	2021-03-04 09:43:29 -05:00
spike.h	riscv: spike: Remove target macro conditionals	2020-12-17 21:56:44 -08:00
virt.h	hw/riscv: migrate fdt field to generic MachineState	2021-03-10 15:34:11 +00:00