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c9410a689f
qemu/target/riscv/insn_trans
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Christoph Müllner c9410a689f RISC-V: Adding XTheadBa ISA extension 
This patch adds support for the XTheadBa ISA extension.
The patch uses the T-Head specific decoder and translation.

Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230131202013.2541053-4-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-02-07 08:19:23 +10:00
..
trans_privileged.c.inc target/riscv: Add itrigger support when icount is not enabled 2023-01-06 10:42:55 +10:00
trans_rva.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_rvb.c.inc target/riscv: rvk: add support for zbkx extension 2022-04-29 10:47:45 +10:00
trans_rvd.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_rvf.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_rvh.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_rvi.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_rvk.c.inc target/riscv: rvk: add support for zksed/zksh extension 2022-04-29 10:47:45 +10:00
trans_rvm.c.inc target/riscv: add support for zmmul extension v0.1 2022-06-10 09:31:42 +10:00
trans_rvv.c.inc target/riscv: Introduce helper_set_rounding_mode_chkfrm 2023-01-20 10:14:14 +10:00
trans_rvzawrs.c.inc RISC-V: Add Zawrs ISA extension support 2023-01-06 10:42:55 +10:00
trans_rvzfh.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_svinval.c.inc target/riscv: Ensure opcode is saved for all relevant instructions 2023-02-07 08:19:23 +10:00
trans_xthead.c.inc RISC-V: Adding XTheadBa ISA extension 2023-02-07 08:19:23 +10:00
trans_xventanacondops.c.inc target/riscv: Add XVentanaCondOps custom extension 2022-02-16 12:24:18 +10:00