ca4f47752a
Power CPUs have an execution control facility that can pause, resume, and cause NMIs, among other things. Add a function that will nmi a CPU and resume it if it was paused, in preparation for implementing the control facility. Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
256 lines
8.8 KiB
C
256 lines
8.8 KiB
C
/*
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* QEMU PowerPC PowerNV various definitions
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*
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* Copyright (c) 2014-2016 BenH, IBM Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef PPC_PNV_H
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#define PPC_PNV_H
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#include "cpu.h"
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#include "hw/boards.h"
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#include "hw/sysbus.h"
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#include "hw/ipmi/ipmi.h"
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#include "hw/ppc/pnv_pnor.h"
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#define TYPE_PNV_CHIP "pnv-chip"
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typedef struct PnvCore PnvCore;
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typedef struct PnvChip PnvChip;
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typedef struct Pnv8Chip Pnv8Chip;
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typedef struct Pnv9Chip Pnv9Chip;
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typedef struct Pnv10Chip Pnv10Chip;
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#define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
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#define PNV_CHIP_TYPE_NAME(cpu_model) cpu_model PNV_CHIP_TYPE_SUFFIX
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#define TYPE_PNV_CHIP_POWER8E PNV_CHIP_TYPE_NAME("power8e_v2.1")
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DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8E,
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TYPE_PNV_CHIP_POWER8E)
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#define TYPE_PNV_CHIP_POWER8 PNV_CHIP_TYPE_NAME("power8_v2.0")
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DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8,
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TYPE_PNV_CHIP_POWER8)
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#define TYPE_PNV_CHIP_POWER8NVL PNV_CHIP_TYPE_NAME("power8nvl_v1.0")
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DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL,
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TYPE_PNV_CHIP_POWER8NVL)
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#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.2")
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DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9,
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TYPE_PNV_CHIP_POWER9)
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#define TYPE_PNV_CHIP_POWER10 PNV_CHIP_TYPE_NAME("power10_v2.0")
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DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10,
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TYPE_PNV_CHIP_POWER10)
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PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id);
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PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir);
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typedef struct PnvPHB PnvPHB;
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#define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv")
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typedef struct PnvMachineClass PnvMachineClass;
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typedef struct PnvMachineState PnvMachineState;
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DECLARE_OBJ_CHECKERS(PnvMachineState, PnvMachineClass,
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PNV_MACHINE, TYPE_PNV_MACHINE)
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struct PnvMachineClass {
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/*< private >*/
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MachineClass parent_class;
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/*< public >*/
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const char *compat;
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int compat_size;
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int max_smt_threads;
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bool quirk_tb_big_core;
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void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt);
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void (*i2c_init)(PnvMachineState *pnv);
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};
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struct PnvMachineState {
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/*< private >*/
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MachineState parent_obj;
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uint32_t initrd_base;
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long initrd_size;
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uint32_t num_chips;
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PnvChip **chips;
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ISABus *isa_bus;
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uint32_t cpld_irqstate;
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IPMIBmc *bmc;
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Notifier powerdown_notifier;
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PnvPnor *pnor;
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hwaddr fw_load_addr;
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bool big_core;
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};
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PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id);
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PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb);
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#define PNV_FDT_ADDR 0x01000000
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#define PNV_TIMEBASE_FREQ 512000000ULL
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void pnv_cpu_do_nmi_resume(CPUState *cs);
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/*
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* BMC helpers
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*/
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void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt);
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void pnv_bmc_powerdown(IPMIBmc *bmc);
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IPMIBmc *pnv_bmc_create(PnvPnor *pnor);
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IPMIBmc *pnv_bmc_find(Error **errp);
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void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
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/*
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* POWER8 MMIO base addresses
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*/
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#define PNV_XSCOM_SIZE 0x800000000ull
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#define PNV_XSCOM_BASE(chip) \
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(0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
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#define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
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#define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull
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#define PNV_OCC_SENSOR_BASE(chip) (PNV_OCC_COMMON_AREA_BASE + \
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PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
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#define PNV_HOMER_SIZE 0x0000000000400000ull
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#define PNV_HOMER_BASE(chip) \
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(0x7ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV_HOMER_SIZE)
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/*
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* XSCOM 0x20109CA defines the ICP BAR:
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*
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* 0:29 : bits 14 to 43 of address to define 1 MB region.
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* 30 : 1 to enable ICP to receive loads/stores against its BAR region
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* 31:63 : Constant 0
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*
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* Usually defined as :
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*
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* 0xffffe00200000000 -> 0x0003ffff80000000
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* 0xffffe00600000000 -> 0x0003ffff80100000
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* 0xffffe02200000000 -> 0x0003ffff80800000
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* 0xffffe02600000000 -> 0x0003ffff80900000
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*/
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#define PNV_ICP_SIZE 0x0000000000100000ull
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#define PNV_ICP_BASE(chip) \
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(0x0003ffff80000000ull + (uint64_t) (chip)->chip_id * PNV_ICP_SIZE)
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#define PNV_PSIHB_SIZE 0x0000000000100000ull
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#define PNV_PSIHB_BASE(chip) \
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(0x0003fffe80000000ull + (uint64_t)(chip)->chip_id * PNV_PSIHB_SIZE)
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#define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull
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#define PNV_PSIHB_FSP_BASE(chip) \
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(0x0003ffe000000000ull + (uint64_t)(chip)->chip_id * \
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PNV_PSIHB_FSP_SIZE)
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/*
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* POWER9 MMIO base addresses
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*/
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#define PNV9_CHIP_BASE(chip, base) \
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((base) + ((uint64_t) (chip)->chip_id << 42))
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#define PNV9_XIVE_VC_SIZE 0x0000008000000000ull
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#define PNV9_XIVE_VC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006010000000000ull)
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#define PNV9_XIVE_PC_SIZE 0x0000001000000000ull
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#define PNV9_XIVE_PC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006018000000000ull)
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#define PNV9_LPCM_SIZE 0x0000000100000000ull
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#define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030000000000ull)
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#define PNV9_PSIHB_SIZE 0x0000000000100000ull
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#define PNV9_PSIHB_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203000000ull)
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#define PNV9_XIVE_IC_SIZE 0x0000000000080000ull
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#define PNV9_XIVE_IC_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203100000ull)
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#define PNV9_XIVE_TM_SIZE 0x0000000000040000ull
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#define PNV9_XIVE_TM_BASE(chip) PNV9_CHIP_BASE(chip, 0x0006030203180000ull)
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#define PNV9_PSIHB_ESB_SIZE 0x0000000000010000ull
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#define PNV9_PSIHB_ESB_BASE(chip) PNV9_CHIP_BASE(chip, 0x00060302031c0000ull)
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#define PNV9_XSCOM_SIZE 0x0000000400000000ull
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#define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull)
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#define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
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#define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull
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#define PNV9_OCC_SENSOR_BASE(chip) (PNV9_OCC_COMMON_AREA_BASE + \
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PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
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#define PNV9_HOMER_SIZE 0x0000000000400000ull
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#define PNV9_HOMER_BASE(chip) \
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(0x203ffd800000ull + ((uint64_t)(chip)->chip_id) * PNV9_HOMER_SIZE)
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/*
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* POWER10 MMIO base addresses - 16TB stride per chip
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*/
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#define PNV10_CHIP_BASE(chip, base) \
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((base) + ((uint64_t) (chip)->chip_id << 44))
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#define PNV10_XSCOM_SIZE 0x0000000400000000ull
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#define PNV10_XSCOM_BASE(chip) PNV10_CHIP_BASE(chip, 0x00603fc00000000ull)
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#define PNV10_LPCM_SIZE 0x0000000100000000ull
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#define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull)
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#define PNV10_XIVE2_IC_SIZE 0x0000000002000000ull
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#define PNV10_XIVE2_IC_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030200000000ull)
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#define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull
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#define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull)
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#define PNV10_PSIHB_SIZE 0x0000000000100000ull
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#define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull)
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#define PNV10_XIVE2_TM_SIZE 0x0000000000040000ull
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#define PNV10_XIVE2_TM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203180000ull)
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#define PNV10_XIVE2_NVC_SIZE 0x0000000008000000ull
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#define PNV10_XIVE2_NVC_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030208000000ull)
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#define PNV10_XIVE2_NVPG_SIZE 0x0000010000000000ull
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#define PNV10_XIVE2_NVPG_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006040000000000ull)
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#define PNV10_XIVE2_ESB_SIZE 0x0000010000000000ull
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#define PNV10_XIVE2_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006050000000000ull)
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#define PNV10_XIVE2_END_SIZE 0x0000020000000000ull
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#define PNV10_XIVE2_END_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006060000000000ull)
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#define PNV10_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
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#define PNV10_OCC_COMMON_AREA_BASE 0x300fff800000ull
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#define PNV10_OCC_SENSOR_BASE(chip) (PNV10_OCC_COMMON_AREA_BASE + \
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PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
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#define PNV10_HOMER_SIZE 0x0000000000400000ull
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#define PNV10_HOMER_BASE(chip) \
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(0x300ffd800000ll + ((uint64_t)(chip)->chip_id) * PNV10_HOMER_SIZE)
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#endif /* PPC_PNV_H */
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