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ppc/pnv: Add a CPU nmi and resume function

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Power CPUs have an execution control facility that can pause, resume,
and cause NMIs, among other things. Add a function that will nmi a CPU
and resume it if it was paused, in preparation for implementing the
control facility.

Reviewed-by: Cédric Le Goater <clg@redhat.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
Nicholas Piggin 2024-07-12 13:16:44 +10:00
parent b1beb69231
commit ca4f47752a
2 changed files with 15 additions and 1 deletions
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14
hw/ppc/pnv.c
View File

@ -2751,11 +2751,23 @@ static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
*/
env->spr[SPR_SRR1] |= SRR1_WAKESCOM;
}
if (arg.host_int == 1) {
cpu_resume(cs);
}
}
/*
* Send a SRESET (NMI) interrupt to the CPU, and resume execution if it was
* paused.
*/
void pnv_cpu_do_nmi_resume(CPUState *cs)
{
async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_HOST_INT(1));
}
static void pnv_cpu_do_nmi(PnvChip *chip, PowerPCCPU *cpu, void *opaque)
{
async_run_on_cpu(CPU(cpu), pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
async_run_on_cpu(CPU(cpu), pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_HOST_INT(0));
}
static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)

2
include/hw/ppc/pnv.h
View File

@ -112,6 +112,8 @@ PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb);
#define PNV_FDT_ADDR 0x01000000
#define PNV_TIMEBASE_FREQ 512000000ULL
void pnv_cpu_do_nmi_resume(CPUState *cs);
/*
* BMC helpers
*/