qemu/hw/riscv
Alex Bennée c65d7080d8 hw/riscv: migrate fdt field to generic MachineState
This is a mechanical change to make the fdt available through
MachineState.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20210303173642.3805-3-alex.bennee@linaro.org>
2021-03-10 15:34:11 +00:00
..
boot.c riscv: Pass RISCVHartArrayState by pointer 2021-01-16 14:34:46 -08:00
Kconfig hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card 2021-03-04 09:43:29 -05:00
meson.build hw/riscv: Always build riscv_hart.c 2020-09-09 15:54:19 -07:00
microchip_pfsoc.c hw/riscv: Drop 'struct MemmapEntry' 2021-03-04 09:43:29 -05:00
numa.c hw/riscv: Add helpers for RISC-V multi-socket NUMA machines 2020-08-25 09:11:35 -07:00
opentitan.c hw/riscv: Drop 'struct MemmapEntry' 2021-03-04 09:43:29 -05:00
riscv_hart.c hw/riscv: hart: Add a new 'resetvec' property 2020-09-09 15:54:18 -07:00
sifive_e.c hw/riscv: Drop 'struct MemmapEntry' 2021-03-04 09:43:29 -05:00
sifive_u.c hw/riscv: Drop 'struct MemmapEntry' 2021-03-04 09:43:29 -05:00
spike.c hw/riscv: Drop 'struct MemmapEntry' 2021-03-04 09:43:29 -05:00
virt.c hw/riscv: migrate fdt field to generic MachineState 2021-03-10 15:34:11 +00:00