qemu/target/arm
Peter Maydell c624ea0fa7 Revert "target/arm: Implement HCR.VI and VF"
This reverts commit 8a0fc3a29f.

The implementation of HCR.VI and VF in that commit is not
correct -- they do not track the overall "is there a pending
VIRQ or VFIQ" status, but whether there is a pending interrupt
due to "this mechanism", ie the hypervisor having set the VI/VF
bits. The overall pending state for VIRQ and VFIQ is effectively
the logical OR of the inbound lines from the GIC with the
VI and VF bits. Commit 8a0fc3a29f would result in pending
VIRQ/VFIQ possibly being lost when the hypervisor wrote to HCR.

As a preliminary to implementing the HCR.VI/VF feature properly,
revert the broken one entirely.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20181109134731.11605-2-peter.maydell@linaro.org
2018-11-13 10:47:59 +00:00
..
arch_dump.c
arm_ldst.h target: Do not include "exec/exec-all.h" if it is not necessary 2018-06-01 14:15:10 +02:00
arm-powerctl.c target-arm: powerctl: Enable HVC when starting CPUs to EL2 2018-10-16 17:14:55 +01:00
arm-powerctl.h
arm-semi.c target/arm: Remove a handful of stray tabs 2018-08-24 13:17:48 +01:00
cpu64.c target/arm: Convert v8.2-fp16 from feature bit to aa64pfr0 test 2018-10-24 07:51:31 +01:00
cpu-qom.h
cpu.c target/arm: Conditionalize some asserts on aarch32 support 2018-11-02 14:08:38 +00:00
cpu.h arm: fix aa64_generate_debug_exceptions to work with EL2 2018-11-13 10:47:59 +00:00
crypto_helper.c target: Do not include "exec/exec-all.h" if it is not necessary 2018-06-01 14:15:10 +02:00
gdbstub64.c
gdbstub.c arm: fix malloc type mismatch 2018-05-31 14:50:52 +01:00
helper-a64.c target/arm: Check HAVE_CMPXCHG128 at translate time 2018-10-18 19:46:53 -07:00
helper-a64.h target/arm: Implement FCMP for fp16 2018-05-15 14:58:43 +01:00
helper-sve.h target/arm: Rewrite vector gather first-fault loads 2018-10-08 14:55:03 +01:00
helper.c Revert "target/arm: Implement HCR.VI and VF" 2018-11-13 10:47:59 +00:00
helper.h target/arm: Add v8M stack checks on ADD/SUB/MOV of SP 2018-10-08 14:55:04 +01:00
idau.h
internals.h target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode 2018-10-24 07:51:36 +01:00
iwmmxt_helper.c target/arm: Untabify iwmmxt_helper.c 2018-08-24 13:17:48 +01:00
kvm32.c target/arm: Add support for VCPU event states 2018-10-24 07:50:16 +01:00
kvm64.c target/arm64: kvm debug set target_el when passing exception to guest 2018-11-13 10:47:59 +00:00
kvm_arm.h target/arm: Add support for VCPU event states 2018-10-24 07:50:16 +01:00
kvm-consts.h
kvm-stub.c
kvm.c target/arm: Add support for VCPU event states 2018-10-24 07:50:16 +01:00
machine.c target/arm: Convert sve from feature bit to aa64pfr0 test 2018-10-24 07:51:29 +01:00
Makefile.objs target/arm: Implement SVE predicate test 2018-05-18 17:48:08 +01:00
monitor.c
neon_helper.c target: Do not include "exec/exec-all.h" if it is not necessary 2018-06-01 14:15:10 +02:00
op_addsub.h
op_helper.c target/arm: New utility function to extract EC from syndrome 2018-10-24 07:51:36 +01:00
psci.c target: Do not include "exec/exec-all.h" if it is not necessary 2018-06-01 14:15:10 +02:00
sve_helper.c target/arm: Pass TCGMemOpIdx to sve memory helpers 2018-10-08 14:55:03 +01:00
sve.decode target/arm: Implement SVE dot product (indexed) 2018-06-29 15:11:15 +01:00
trace-events target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route 2018-05-04 18:52:58 +01:00
translate-a64.c target/arm: Remove can't-happen if() from handle_vec_simd_shli() 2018-11-06 11:32:13 +00:00
translate-a64.h target/arm: Extend vec_reg_offset to larger sizes 2018-06-15 15:23:34 +01:00
translate-sve.c decodetree: Remove "insn" argument from trans_* expanders 2018-10-31 16:48:54 +00:00
translate.c target/arm: Reorg NEON VLD/VST single element to one lane 2018-10-24 07:51:37 +01:00
translate.h target/arm: Use gvec for NEON_3R_VTST_VCEQ, NEON_3R_VCGT, NEON_3R_VCGE 2018-10-24 07:51:37 +01:00
vec_helper.c target/arm: Implement SVE dot product (indexed) 2018-06-29 15:11:15 +01:00