Peter Maydell c624ea0fa7 Revert "target/arm: Implement HCR.VI and VF" ... This reverts commit 8a0fc3a29f. The implementation of HCR.VI and VF in that commit is not correct -- they do not track the overall "is there a pending VIRQ or VFIQ" status, but whether there is a pending interrupt due to "this mechanism", ie the hypervisor having set the VI/VF bits. The overall pending state for VIRQ and VFIQ is effectively the logical OR of the inbound lines from the GIC with the VI and VF bits. Commit 8a0fc3a29f would result in pending VIRQ/VFIQ possibly being lost when the hypervisor wrote to HCR. As a preliminary to implementing the HCR.VI/VF feature properly, revert the broken one entirely. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20181109134731.11605-2-peter.maydell@linaro.org		2018-11-13 10:47:59 +00:00
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alpha
arm	Revert "target/arm: Implement HCR.VI and VF"	2018-11-13 10:47:59 +00:00
cris
hppa
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microblaze
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moxie
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sh4
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tilegx
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