Alistair Francis c407784291 hw/riscv: Add a riscv_is_32_bit() function ... Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-id: 4c6a85dfb6dd470aa79356ebc1b02f479c2758e0.1602634524.git.alistair.francis@wdc.com		2020-10-22 12:00:22 -07:00
..
boot.c	hw/riscv: Add a riscv_is_32_bit() function	2020-10-22 12:00:22 -07:00
Kconfig	hw/riscv: Sort the Kconfig options in alphabetical order	2020-09-09 15:54:19 -07:00
meson.build	hw/riscv: Always build riscv_hart.c	2020-09-09 15:54:19 -07:00
microchip_pfsoc.c	hw/riscv: Move sifive_plic model to hw/intc	2020-09-09 15:54:19 -07:00
numa.c	hw/riscv: Add helpers for RISC-V multi-socket NUMA machines	2020-08-25 09:11:35 -07:00
opentitan.c	target/riscv: cpu: Set reset vector based on the configured property value	2020-09-09 15:54:18 -07:00
riscv_hart.c	hw/riscv: hart: Add a new 'resetvec' property	2020-09-09 15:54:18 -07:00
sifive_e.c	sifive_e: Register "revb" as class property	2020-09-22 16:48:29 -04:00
sifive_u.c	hw/riscv: sifive_u: Allow specifying the CPU	2020-10-22 12:00:22 -07:00
spike.c	hw/riscv: Move riscv_htif model to hw/char	2020-09-09 15:54:19 -07:00
virt.c	hw/riscv: Move sifive_test model to hw/misc	2020-09-09 15:54:19 -07:00