e2fd695e9d
The djMEMC controller is used to store information related to the physical memory configuration. Co-developed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20231004083806.757242-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
136 lines
3.5 KiB
C
136 lines
3.5 KiB
C
/*
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* djMEMC, macintosh memory and interrupt controller
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* (Quadra 610/650/800 & Centris 610/650)
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*
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* https://mac68k.info/wiki/display/mac68k/djMEMC+Information
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "migration/vmstate.h"
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#include "hw/misc/djmemc.h"
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#include "hw/qdev-properties.h"
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#include "trace.h"
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#define DJMEMC_INTERLEAVECONF 0x0
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#define DJMEMC_BANK0CONF 0x4
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#define DJMEMC_BANK1CONF 0x8
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#define DJMEMC_BANK2CONF 0xc
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#define DJMEMC_BANK3CONF 0x10
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#define DJMEMC_BANK4CONF 0x14
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#define DJMEMC_BANK5CONF 0x18
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#define DJMEMC_BANK6CONF 0x1c
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#define DJMEMC_BANK7CONF 0x20
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#define DJMEMC_BANK8CONF 0x24
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#define DJMEMC_BANK9CONF 0x28
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#define DJMEMC_MEMTOP 0x2c
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#define DJMEMC_CONFIG 0x30
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#define DJMEMC_REFRESH 0x34
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static uint64_t djmemc_read(void *opaque, hwaddr addr, unsigned size)
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{
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DJMEMCState *s = opaque;
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uint64_t val = 0;
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switch (addr) {
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case DJMEMC_INTERLEAVECONF:
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case DJMEMC_BANK0CONF ... DJMEMC_BANK9CONF:
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case DJMEMC_MEMTOP:
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case DJMEMC_CONFIG:
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case DJMEMC_REFRESH:
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val = s->regs[addr >> 2];
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "djMEMC: unimplemented read addr=0x%"PRIx64
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" val=0x%"PRIx64 " size=%d\n",
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addr, val, size);
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}
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trace_djmemc_read(addr, val, size);
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return val;
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}
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static void djmemc_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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{
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DJMEMCState *s = opaque;
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trace_djmemc_write(addr, val, size);
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switch (addr) {
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case DJMEMC_INTERLEAVECONF:
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case DJMEMC_BANK0CONF ... DJMEMC_BANK9CONF:
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case DJMEMC_MEMTOP:
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case DJMEMC_CONFIG:
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case DJMEMC_REFRESH:
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s->regs[addr >> 2] = val;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "djMEMC: unimplemented write addr=0x%"PRIx64
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" val=0x%"PRIx64 " size=%d\n",
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addr, val, size);
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}
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}
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static const MemoryRegionOps djmemc_mmio_ops = {
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.read = djmemc_read,
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.write = djmemc_write,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void djmemc_init(Object *obj)
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{
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DJMEMCState *s = DJMEMC(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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memory_region_init_io(&s->mem_regs, obj, &djmemc_mmio_ops, s, "djMEMC",
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DJMEMC_SIZE);
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sysbus_init_mmio(sbd, &s->mem_regs);
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}
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static void djmemc_reset_hold(Object *obj)
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{
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DJMEMCState *s = DJMEMC(obj);
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memset(s->regs, 0, sizeof(s->regs));
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}
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static const VMStateDescription vmstate_djmemc = {
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.name = "djMEMC",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, DJMEMCState, DJMEMC_NUM_REGS),
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VMSTATE_END_OF_LIST()
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}
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};
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static void djmemc_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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ResettableClass *rc = RESETTABLE_CLASS(oc);
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dc->vmsd = &vmstate_djmemc;
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rc->phases.hold = djmemc_reset_hold;
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}
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static const TypeInfo djmemc_info_types[] = {
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{
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.name = TYPE_DJMEMC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(DJMEMCState),
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.instance_init = djmemc_init,
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.class_init = djmemc_class_init,
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},
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};
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DEFINE_TYPES(djmemc_info_types)
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