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q800: add djMEMC memory controller

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The djMEMC controller is used to store information related to the physical memory
configuration.

Co-developed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20231004083806.757242-3-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
This commit is contained in:
Mark Cave-Ayland 2023-10-04 09:37:48 +01:00 committed by Laurent Vivier
parent d43e967f69
commit e2fd695e9d
9 changed files with 188 additions and 0 deletions
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2
MAINTAINERS
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@ -1229,6 +1229,7 @@ F: hw/misc/mac_via.c
F: hw/nubus/*
F: hw/display/macfb.c
F: hw/block/swim.c
F: hw/misc/djmemc.c
F: hw/m68k/bootinfo.h
F: include/standard-headers/asm-m68k/bootinfo.h
F: include/standard-headers/asm-m68k/bootinfo-mac.h
@ -1238,6 +1239,7 @@ F: include/hw/display/macfb.h
F: include/hw/block/swim.h
F: include/hw/m68k/q800.h
F: include/hw/m68k/q800-glue.h
F: include/hw/misc/djmemc.h
virt
M: Laurent Vivier <laurent@vivier.eu>

1
hw/m68k/Kconfig
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@ -23,6 +23,7 @@ config Q800
select ESP
select DP8393X
select OR_IRQ
select DJMEMC
config M68K_VIRT
bool

10
hw/m68k/q800.c
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@ -40,6 +40,7 @@
#include "hw/m68k/q800.h"
#include "hw/m68k/q800-glue.h"
#include "hw/misc/mac_via.h"
#include "hw/misc/djmemc.h"
#include "hw/input/adb.h"
#include "hw/nubus/mac-nubus-bridge.h"
#include "hw/display/macfb.h"
@ -66,6 +67,7 @@
#define SONIC_PROM_BASE (IO_BASE + 0x08000)
#define SONIC_BASE (IO_BASE + 0x0a000)
#define SCC_BASE (IO_BASE + 0x0c020)
#define DJMEMC_BASE (IO_BASE + 0x0e000)
#define ESP_BASE (IO_BASE + 0x10000)
#define ESP_PDMA (IO_BASE + 0x10100)
#define ASC_BASE (IO_BASE + 0x14000)
@ -257,6 +259,14 @@ static void q800_machine_init(MachineState *machine)
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&m->glue), &error_fatal);
/* djMEMC memory controller */
object_initialize_child(OBJECT(machine), "djmemc", &m->djmemc,
TYPE_DJMEMC);
sysbus = SYS_BUS_DEVICE(&m->djmemc);
sysbus_realize_and_unref(sysbus, &error_fatal);
memory_region_add_subregion(&m->macio, DJMEMC_BASE - IO_BASE,
sysbus_mmio_get_region(sysbus, 0));
/* VIA 1 */
object_initialize_child(OBJECT(machine), "via1", &m->via1,
TYPE_MOS6522_Q800_VIA1);

3
hw/misc/Kconfig
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@ -186,4 +186,7 @@ config AXP2XX_PMU
bool
depends on I2C
config DJMEMC
bool
source macio/Kconfig

135
hw/misc/djmemc.c Normal file
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@ -0,0 +1,135 @@
/*
* djMEMC, macintosh memory and interrupt controller
* (Quadra 610/650/800 & Centris 610/650)
*
* https://mac68k.info/wiki/display/mac68k/djMEMC+Information
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "migration/vmstate.h"
#include "hw/misc/djmemc.h"
#include "hw/qdev-properties.h"
#include "trace.h"
#define DJMEMC_INTERLEAVECONF 0x0
#define DJMEMC_BANK0CONF 0x4
#define DJMEMC_BANK1CONF 0x8
#define DJMEMC_BANK2CONF 0xc
#define DJMEMC_BANK3CONF 0x10
#define DJMEMC_BANK4CONF 0x14
#define DJMEMC_BANK5CONF 0x18
#define DJMEMC_BANK6CONF 0x1c
#define DJMEMC_BANK7CONF 0x20
#define DJMEMC_BANK8CONF 0x24
#define DJMEMC_BANK9CONF 0x28
#define DJMEMC_MEMTOP 0x2c
#define DJMEMC_CONFIG 0x30
#define DJMEMC_REFRESH 0x34
static uint64_t djmemc_read(void *opaque, hwaddr addr, unsigned size)
{
DJMEMCState *s = opaque;
uint64_t val = 0;
switch (addr) {
case DJMEMC_INTERLEAVECONF:
case DJMEMC_BANK0CONF ... DJMEMC_BANK9CONF:
case DJMEMC_MEMTOP:
case DJMEMC_CONFIG:
case DJMEMC_REFRESH:
val = s->regs[addr >> 2];
break;
default:
qemu_log_mask(LOG_UNIMP, "djMEMC: unimplemented read addr=0x%"PRIx64
" val=0x%"PRIx64 " size=%d\n",
addr, val, size);
}
trace_djmemc_read(addr, val, size);
return val;
}
static void djmemc_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
{
DJMEMCState *s = opaque;
trace_djmemc_write(addr, val, size);
switch (addr) {
case DJMEMC_INTERLEAVECONF:
case DJMEMC_BANK0CONF ... DJMEMC_BANK9CONF:
case DJMEMC_MEMTOP:
case DJMEMC_CONFIG:
case DJMEMC_REFRESH:
s->regs[addr >> 2] = val;
break;
default:
qemu_log_mask(LOG_UNIMP, "djMEMC: unimplemented write addr=0x%"PRIx64
" val=0x%"PRIx64 " size=%d\n",
addr, val, size);
}
}
static const MemoryRegionOps djmemc_mmio_ops = {
.read = djmemc_read,
.write = djmemc_write,
.impl = {
.min_access_size = 4,
.max_access_size = 4,
},
.endianness = DEVICE_BIG_ENDIAN,
};
static void djmemc_init(Object *obj)
{
DJMEMCState *s = DJMEMC(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
memory_region_init_io(&s->mem_regs, obj, &djmemc_mmio_ops, s, "djMEMC",
DJMEMC_SIZE);
sysbus_init_mmio(sbd, &s->mem_regs);
}
static void djmemc_reset_hold(Object *obj)
{
DJMEMCState *s = DJMEMC(obj);
memset(s->regs, 0, sizeof(s->regs));
}
static const VMStateDescription vmstate_djmemc = {
.name = "djMEMC",
.version_id = 1,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, DJMEMCState, DJMEMC_NUM_REGS),
VMSTATE_END_OF_LIST()
}
};
static void djmemc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
dc->vmsd = &vmstate_djmemc;
rc->phases.hold = djmemc_reset_hold;
}
static const TypeInfo djmemc_info_types[] = {
{
.name = TYPE_DJMEMC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(DJMEMCState),
.instance_init = djmemc_init,
.class_init = djmemc_class_init,
},
};
DEFINE_TYPES(djmemc_info_types)

1
hw/misc/meson.build
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@ -20,6 +20,7 @@ system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_ras.c'))
# Mac devices
system_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c'))
system_ss.add(when: 'CONFIG_DJMEMC', if_true: files('djmemc.c'))
# virt devices
system_ss.add(when: 'CONFIG_VIRT_CTRL', if_true: files('virt_ctrl.c'))

4
hw/misc/trace-events
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@ -301,3 +301,7 @@ virt_ctrl_instance_init(void *dev) "ctrl: %p"
lasi_chip_mem_valid(uint64_t addr, uint32_t val) "access to addr 0x%"PRIx64" is %d"
lasi_chip_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
lasi_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x"
# djmemc.c
djmemc_read(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u"
djmemc_write(int reg, uint64_t value, unsigned int size) "reg=0x%x value=0x%"PRIx64" size=%u"

2
include/hw/m68k/q800.h
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@ -36,6 +36,7 @@
#include "hw/block/swim.h"
#include "hw/nubus/mac-nubus-bridge.h"
#include "hw/display/macfb.h"
#include "hw/misc/djmemc.h"
/*
* The main Q800 machine
@ -56,6 +57,7 @@ struct Q800MachineState {
Swim swim;
MacNubusBridge mac_nubus_bridge;
MacfbNubusState macfb;
DJMEMCState djmemc;
MemoryRegion macio;
MemoryRegion macio_alias;
};

30
include/hw/misc/djmemc.h Normal file
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@ -0,0 +1,30 @@
/*
* djMEMC, macintosh memory and interrupt controller
* (Quadra 610/650/800 & Centris 610/650)
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#ifndef HW_MISC_DJMEMC_H
#define HW_MISC_DJMEMC_H
#include "hw/sysbus.h"
#define DJMEMC_SIZE 0x2000
#define DJMEMC_NUM_REGS (0x38 / sizeof(uint32_t))
#define DJMEMC_MAXBANKS 10
struct DJMEMCState {
SysBusDevice parent_obj;
MemoryRegion mem_regs;
/* Memory controller */
uint32_t regs[DJMEMC_NUM_REGS];
};
#define TYPE_DJMEMC "djMEMC"
OBJECT_DECLARE_SIMPLE_TYPE(DJMEMCState, DJMEMC);
#endif