.. |
insn_trans
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target/riscv: rvv: Add mask agnostic for vx instructions
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2022-09-07 09:18:33 +02:00 |
arch_dump.c
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target-riscv: support QMP dump-guest-memory
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2021-03-04 09:43:29 -05:00 |
bitmanip_helper.c
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target/riscv: rvk: add support for zbkx extension
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2022-04-29 10:47:45 +10:00 |
common-semi-target.h
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semihosting: Split out common-semi-target.h
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2022-06-28 04:35:07 +05:30 |
cpu_bits.h
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target/riscv: Update default priority table for local interrupts
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2022-07-03 10:03:20 +10:00 |
cpu_helper.c
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target/riscv: rvv: Add mask agnostic for vv instructions
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2022-09-07 09:18:32 +02:00 |
cpu_user.h
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Supply missing header guards
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2019-06-12 13:20:21 +02:00 |
cpu-param.h
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Normalize header guard symbol definition
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2022-05-11 16:50:26 +02:00 |
cpu.c
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target/riscv: Fix checks in hmode/hmode32
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2022-09-07 09:18:32 +02:00 |
cpu.h
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target/riscv: rvv: Add mask agnostic for vv instructions
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2022-09-07 09:18:32 +02:00 |
crypto_helper.c
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target/riscv: rvk: add support for zksed/zksh extension
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2022-04-29 10:47:45 +10:00 |
csr.c
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target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_check
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2022-09-07 09:18:32 +02:00 |
debug.c
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target/riscv/debug.c: keep experimental rv128 support working
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2022-06-10 09:31:42 +10:00 |
debug.h
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target/riscv: csr: Hook debug CSR read/write
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2022-04-22 10:35:16 +10:00 |
fpu_helper.c
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target/riscv: add support for zhinx/zhinxmin
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2022-03-03 13:14:50 +10:00 |
gdbstub.c
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target/riscv: correct "code should not be reached" for x-rv128
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2022-02-16 12:24:18 +10:00 |
helper.h
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target/riscv: rvk: add support for zksed/zksh extension
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2022-04-29 10:47:45 +10:00 |
insn16.decode
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target/riscv: fix shifts shamt value for rv128c
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2022-09-07 09:18:32 +02:00 |
insn32.decode
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target/riscv: rvk: add support for zksed/zksh extension
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2022-04-29 10:47:45 +10:00 |
instmap.h
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target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
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2022-09-07 09:18:32 +02:00 |
internals.h
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target/riscv: rvv: Add mask agnostic for vv instructions
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2022-09-07 09:18:32 +02:00 |
Kconfig
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meson: Introduce target-specific Kconfig
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2021-07-09 18:21:34 +02:00 |
kvm_riscv.h
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target/riscv: Support setting external interrupt by KVM
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2022-01-21 15:52:56 +10:00 |
kvm-stub.c
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target/riscv: Support setting external interrupt by KVM
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2022-01-21 15:52:56 +10:00 |
kvm.c
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Remove qemu-common.h include from most units
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2022-04-06 14:31:55 +02:00 |
m128_helper.c
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target/riscv: support for 128-bit M extension
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2022-01-08 15:46:10 +10:00 |
machine.c
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target/riscv: Support mcycle/minstret write operation
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2022-07-03 10:03:20 +10:00 |
meson.build
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meson: remove dead code
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2022-09-01 07:42:37 +02:00 |
monitor.c
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target/riscv: Fix incorrect PTE merge in walk_pte
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2022-04-29 10:47:46 +10:00 |
op_helper.c
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target/riscv: rvk: add CSR support for Zkr
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2022-04-29 10:47:45 +10:00 |
pmp.c
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target/riscv/pmp: guard against PMP ranges with a negative size
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2022-07-03 10:03:20 +10:00 |
pmp.h
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target/riscv: rvk: add CSR support for Zkr
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2022-04-29 10:47:45 +10:00 |
pmu.c
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target/riscv: Support mcycle/minstret write operation
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2022-07-03 10:03:20 +10:00 |
pmu.h
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target/riscv: Support mcycle/minstret write operation
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2022-07-03 10:03:20 +10:00 |
sbi_ecall_interface.h
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Clean up ill-advised or unusual header guards
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2022-05-11 16:50:01 +02:00 |
trace-events
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target/riscv: Add ePMP CSR access functions
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2021-05-11 20:02:06 +10:00 |
trace.h
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trace: switch position of headers to what Meson requires
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2020-08-21 06:18:24 -04:00 |
translate.c
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target/riscv: rvv: Add mask agnostic for vv instructions
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2022-09-07 09:18:32 +02:00 |
vector_helper.c
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target/riscv: rvv: Add mask agnostic for vx instructions
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2022-09-07 09:18:33 +02:00 |
XVentanaCondOps.decode
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target/riscv: Add XVentanaCondOps custom extension
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2022-02-16 12:24:18 +10:00 |