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bce8a342a1
qemu/target/riscv/insn_trans
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Bastian Koppelmann bce8a342a1 target/riscv: Remove manual decoding from gen_store() 
With decodetree we don't need to convert RISC-V opcodes into to MemOps
as the old gen_store() did.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
2019-03-13 10:40:50 +01:00
..
trans_privileged.inc.c target/riscv: Convert RV priv insns to decodetree 2019-03-13 10:34:06 +01:00
trans_rva.inc.c target/riscv: Convert RV64A insns to decodetree 2019-03-13 10:34:06 +01:00
trans_rvc.inc.c target/riscv: Convert quadrant 2 of RVXC insns to decodetree 2019-03-13 10:40:46 +01:00
trans_rvd.inc.c target/riscv: Convert RV64D insns to decodetree 2019-03-13 10:34:06 +01:00
trans_rvf.inc.c target/riscv: Convert RV64F insns to decodetree 2019-03-13 10:34:06 +01:00
trans_rvi.inc.c target/riscv: Remove manual decoding from gen_store() 2019-03-13 10:40:50 +01:00
trans_rvm.inc.c target/riscv: Convert RVXM insns to decodetree 2019-03-13 10:34:06 +01:00