Rajnesh Kanwal b901c7eb70 target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled ... With H-Ext supported, VS bits are all hardwired to one in MIDELEG denoting always delegated interrupts. This is being done in rmw_mideleg but given mideleg is used in other places when routing interrupts this change initializes it in riscv_cpu_realize to be on the safe side. Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20231016111736.28721-4-rkanwal@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2023-11-07 11:02:17 +10:00
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meson.build	target/riscv: introduce TCG AccelCPUClass	2023-10-12 11:55:21 +10:00
tcg-cpu.c	target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled	2023-11-07 11:02:17 +10:00
tcg-cpu.h	target/riscv: move riscv_cpu_validate_set_extensions() to tcg-cpu.c	2023-10-12 11:57:46 +10:00