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Rajnesh Kanwal b901c7eb70 target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled 
With H-Ext supported, VS bits are all hardwired to one in MIDELEG
denoting always delegated interrupts. This is being done in rmw_mideleg
but given mideleg is used in other places when routing interrupts
this change initializes it in riscv_cpu_realize to be on the safe side.

Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231016111736.28721-4-rkanwal@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2023-11-07 11:02:17 +10:00
..
insn_trans
target/riscv: rename ext_icboz to ext_zicboz
2023-11-07 11:02:17 +10:00
kvm
target/riscv: rename ext_icboz to ext_zicboz
2023-11-07 11:02:17 +10:00
tcg
target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled
2023-11-07 11:02:17 +10:00
arch_dump.c
…
bitmanip_helper.c
…
common-semi-target.h
…
cpu_bits.h
target/riscv: Update CSR bits name for svadu extension
2023-09-11 11:45:55 +10:00
cpu_cfg.h
target/riscv: rename ext_icboz to ext_zicboz
2023-11-07 11:02:17 +10:00
cpu_helper.c
target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.
2023-11-07 11:02:17 +10:00
cpu_user.h
…
cpu_vendorid.h
…
cpu-param.h
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cpu-qom.h
target/riscv: add 'max' CPU type
2023-10-12 11:39:33 +10:00
cpu.c
target/riscv: rename ext_icboz to ext_zicboz
2023-11-07 11:02:17 +10:00
cpu.h
target/riscv: deprecate capital 'Z' CPU properties
2023-10-12 12:42:41 +10:00
crypto_helper.c
target/riscv: Use accelerated helper for AES64KS1I
2023-09-11 11:45:55 +10:00
csr.c
target/riscv: Without H-mode mask all HS mode inturrupts in mie.
2023-11-07 11:02:17 +10:00
debug.c
target/riscv: Allocate itrigger timers only once
2023-09-11 11:45:55 +10:00
debug.h
target/riscv: Allocate itrigger timers only once
2023-09-11 11:45:55 +10:00
fpu_helper.c
…
gdbstub.c
target/riscv: rename ext_icsr to ext_zicsr
2023-11-07 11:02:17 +10:00
helper.h
target/riscv: Add Zvksed ISA extension support
2023-09-11 11:45:55 +10:00
insn16.decode
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insn32.decode
target/riscv: Add Zvksed ISA extension support
2023-09-11 11:45:55 +10:00
instmap.h
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internals.h
…
Kconfig
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m128_helper.c
…
machine.c
…
meson.build
target/riscv: move KVM only files to kvm subdir
2023-10-12 12:20:24 +10:00
monitor.c
…
op_helper.c
…
pmp.c
target/riscv/pmp.c: respect mseccfg.RLB for pmpaddrX changes
2023-09-11 11:45:55 +10:00
pmp.h
…
pmu.c
…
pmu.h
…
riscv-qmp-cmds.c
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sbi_ecall_interface.h
…
time_helper.c
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time_helper.h
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trace-events
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trace.h
…
translate.c
accel/tcg: Replace CPUState.env_ptr with cpu_env()
2023-10-04 11:03:54 -07:00
vcrypto_helper.c
target/riscv: Add Zvksed ISA extension support
2023-09-11 11:45:55 +10:00
vector_helper.c
target/riscv: Fix vfwmaccbf16.vf
2023-10-12 12:50:13 +10:00
vector_internals.c
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vector_internals.h
target/riscv: Refactor some of the generic vector functionality
2023-09-11 11:45:55 +10:00
xthead.decode
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XVentanaCondOps.decode
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zce_helper.c
…