Richard Henderson b64ee454a4 target/arm: Introduce PREDDESC field definitions ... SVE predicate operations cannot use the "usual" simd_desc encoding, because the lengths are not a multiple of 8. But we were abusing the SIMD_* fields to store values anyway. This abuse broke when SIMD_OPRSZ_BITS was modified in e2e7168a21. Introduce a new set of field definitions for exclusive use of predicates, so that it is obvious what kind of predicate we are manipulating. To be used in future patches. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210113062650.593824-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2021-01-19 14:38:52 +00:00
..
a32-uncond.decode	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
a32.decode	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
arch_dump.c	target/arm: add spaces around operator	2020-11-10 11:03:47 +00:00
arm_ldst.h	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
arm-powerctl.c
arm-powerctl.h
cpu64.c	target/arm: enable Secure EL2 in max CPU	2021-01-19 14:38:52 +00:00
cpu_tcg.c	target/arm: Implement Cortex-M55 model	2021-01-08 15:13:38 +00:00
cpu-param.h	target/arm: add MMU stage 1 for Secure EL2	2021-01-19 14:38:51 +00:00
cpu-qom.h	qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros	2020-09-18 14:12:32 -04:00
cpu.c	target/arm: Implement SCR_EL2.EEL2	2021-01-19 14:38:52 +00:00
cpu.h	target/arm: Implement SCR_EL2.EEL2	2021-01-19 14:38:52 +00:00
crypto_helper.c	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
debug_helper.c
gdbstub64.c	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
gdbstub.c	target/arm: use official org.gnu.gdb.aarch64.sve layout for registers	2021-01-18 10:05:06 +00:00
helper-a64.c	target/arm: use arm_is_el2_enabled() where applicable	2021-01-19 14:38:51 +00:00
helper-a64.h	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
helper-sve.h	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
helper.c	target/arm: refactor vae1_tlbmask()	2021-01-19 14:38:52 +00:00
helper.h	target/arm: Fix neon VTBL/VTBX for len > 1	2020-11-10 11:03:48 +00:00
idau.h
internals.h	target/arm: Introduce PREDDESC field definitions	2021-01-19 14:38:52 +00:00
iwmmxt_helper.c	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
kvm64.c	hw/arm/virt: Implement kvm-steal-time	2020-10-08 15:24:32 +01:00
kvm_arm.h	hw/arm/virt: Implement kvm-steal-time	2020-10-08 15:24:32 +01:00
kvm-consts.h
kvm-stub.c
kvm.c	hw/arm/virt: Implement kvm-steal-time	2020-10-08 15:24:32 +01:00
m_helper.c	semihosting: Change common-semi API to be architecture-independent	2021-01-18 10:05:06 +00:00
m-nocp.decode	target/arm: Implement new v8.1M VLLDM and VLSTM encodings	2020-12-10 11:44:56 +00:00
machine.c	migration: Replace migration's JSON writer by the general one	2020-12-19 10:39:16 +01:00
meson.build	semihosting: Move ARM semihosting code to shared directories	2021-01-18 10:05:06 +00:00
monitor.c	target/arm: Add cpu properties to control pauth	2021-01-19 14:38:51 +00:00
mte_helper.c	target/arm: Fix reported EL for mte_check_fail	2020-10-20 16:12:00 +01:00
neon_helper.c
neon-dp.decode	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
neon-ls.decode	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
neon-shared.decode	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
op_addsub.h
op_helper.c	target/arm: add 64-bit S-EL2 to EL exception table	2021-01-19 14:38:51 +00:00
pauth_helper.c	target/arm: Implement an IMPDEF pauth algorithm	2021-01-19 14:38:51 +00:00
psci.c
sve_helper.c	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
sve.decode	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
t16.decode	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
t32.decode	target/arm: Implement M-profile "minimal RAS implementation"	2020-12-10 11:44:56 +00:00
tlb_helper.c	target/arm: set HPFAR_EL2.NS on secure stage 2 faults	2021-01-19 14:38:52 +00:00
trace-events
trace.h
translate-a64.c	target/arm: add MMU stage 1 for Secure EL2	2021-01-19 14:38:51 +00:00
translate-a64.h	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
translate-neon.c.inc	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
translate-sve.c	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
translate-vfp.c.inc	target/arm: Implement FPCXT_NS fp system register	2021-01-08 15:13:38 +00:00
translate.c	target/arm: Implement SCR_EL2.EEL2	2021-01-19 14:38:52 +00:00
translate.h
vec_helper.c	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
vec_internal.h	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
vfp_helper.c	target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension	2020-10-20 16:12:01 +01:00
vfp-uncond.decode	arm tcg cpus: Fix Lesser GPL version number	2020-11-15 16:42:14 +01:00
vfp.decode	target/arm: Implement VLDR/VSTR system register	2020-12-10 11:44:55 +00:00