target/arm: use arm_is_el2_enabled() where applicable
Do not assume that EL2 is available in and only in non-secure context. That equivalence is broken by ARMv8.4-SEL2. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-3-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -2210,7 +2210,7 @@ static inline bool arm_el_is_aa64(CPUARMState *env, int el)
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return aa64;
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}
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if (arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure_below_el3(env)) {
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if (arm_is_el2_enabled(env)) {
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aa64 = aa64 && (env->cp15.hcr_el2 & HCR_RW);
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}
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@ -3154,7 +3154,7 @@ static inline int arm_debug_target_el(CPUARMState *env)
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bool secure = arm_is_secure(env);
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bool route_to_el2 = false;
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if (arm_feature(env, ARM_FEATURE_EL2) && !secure) {
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if (arm_is_el2_enabled(env)) {
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route_to_el2 = env->cp15.hcr_el2 & HCR_TGE ||
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env->cp15.mdcr_el2 & MDCR_TDE;
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}
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@ -972,8 +972,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
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if (new_el == -1) {
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goto illegal_return;
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}
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if (new_el > cur_el
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|| (new_el == 2 && !arm_feature(env, ARM_FEATURE_EL2))) {
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if (new_el > cur_el || (new_el == 2 && !arm_is_el2_enabled(env))) {
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/* Disallow return to an EL which is unimplemented or higher
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* than the current one.
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*/
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@ -985,11 +984,6 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
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goto illegal_return;
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}
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if (new_el == 2 && arm_is_secure_below_el3(env)) {
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/* Return to the non-existent secure-EL2 */
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goto illegal_return;
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}
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if (new_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) {
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goto illegal_return;
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}
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@ -1049,8 +1049,8 @@ static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
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{
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if (arm_feature(env, ARM_FEATURE_V8)) {
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/* Check if CPACR accesses are to be trapped to EL2 */
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if (arm_current_el(env) == 1 &&
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(env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) {
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if (arm_current_el(env) == 1 && arm_is_el2_enabled(env) &&
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(env->cp15.cptr_el[2] & CPTR_TCPAC)) {
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return CP_ACCESS_TRAP_EL2;
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/* Check if CPACR accesses are to be trapped to EL3 */
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} else if (arm_current_el(env) < 3 &&
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@ -2520,7 +2520,7 @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
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bool isread)
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{
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unsigned int cur_el = arm_current_el(env);
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bool secure = arm_is_secure(env);
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bool has_el2 = arm_is_el2_enabled(env);
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uint64_t hcr = arm_hcr_el2_eff(env);
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switch (cur_el) {
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@ -2544,8 +2544,7 @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
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}
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} else {
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/* If HCR_EL2.<E2H> == 0: check CNTHCTL_EL2.EL1PCEN. */
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if (arm_feature(env, ARM_FEATURE_EL2) &&
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timeridx == GTIMER_PHYS && !secure &&
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if (has_el2 && timeridx == GTIMER_PHYS &&
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!extract32(env->cp15.cnthctl_el2, 1, 1)) {
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return CP_ACCESS_TRAP_EL2;
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}
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@ -2554,8 +2553,7 @@ static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
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case 1:
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/* Check CNTHCTL_EL2.EL1PCTEN, which changes location based on E2H. */
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if (arm_feature(env, ARM_FEATURE_EL2) &&
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timeridx == GTIMER_PHYS && !secure &&
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if (has_el2 && timeridx == GTIMER_PHYS &&
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(hcr & HCR_E2H
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? !extract32(env->cp15.cnthctl_el2, 10, 1)
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: !extract32(env->cp15.cnthctl_el2, 0, 1))) {
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@ -2570,7 +2568,7 @@ static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
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bool isread)
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{
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unsigned int cur_el = arm_current_el(env);
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bool secure = arm_is_secure(env);
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bool has_el2 = arm_is_el2_enabled(env);
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uint64_t hcr = arm_hcr_el2_eff(env);
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switch (cur_el) {
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@ -2591,8 +2589,7 @@ static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
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/* fall through */
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case 1:
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if (arm_feature(env, ARM_FEATURE_EL2) &&
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timeridx == GTIMER_PHYS && !secure) {
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if (has_el2 && timeridx == GTIMER_PHYS) {
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if (hcr & HCR_E2H) {
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/* If HCR_EL2.<E2H,TGE> == '10': check CNTHCTL_EL2.EL1PTEN. */
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if (!extract32(env->cp15.cnthctl_el2, 11, 1)) {
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@ -4248,11 +4245,9 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] = {
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static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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ARMCPU *cpu = env_archcpu(env);
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unsigned int cur_el = arm_current_el(env);
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bool secure = arm_is_secure(env);
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if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
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if (arm_is_el2_enabled(env) && cur_el == 1) {
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return env->cp15.vpidr_el2;
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}
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return raw_read(env, ri);
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@ -4279,9 +4274,8 @@ static uint64_t mpidr_read_val(CPUARMState *env)
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static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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unsigned int cur_el = arm_current_el(env);
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bool secure = arm_is_secure(env);
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if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
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if (arm_is_el2_enabled(env) && cur_el == 1) {
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return env->cp15.vmpidr_el2;
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}
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return mpidr_read_val(env);
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@ -5348,7 +5342,7 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env)
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{
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uint64_t ret = env->cp15.hcr_el2;
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if (arm_is_secure_below_el3(env)) {
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if (!arm_is_el2_enabled(env)) {
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/*
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* "This register has no effect if EL2 is not enabled in the
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* current Security state". This is ARMv8.4-SecEL2 speak for
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@ -6145,7 +6139,7 @@ int sve_exception_el(CPUARMState *env, int el)
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/* CPTR_EL2. Since TZ and TFP are positive,
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* they will be zero when EL2 is not present.
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*/
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if (el <= 2 && !arm_is_secure_below_el3(env)) {
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if (el <= 2 && arm_is_el2_enabled(env)) {
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if (env->cp15.cptr_el[2] & CPTR_TZ) {
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return 2;
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}
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@ -8720,8 +8714,7 @@ static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
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}
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return 0;
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case ARM_CPU_MODE_HYP:
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return !arm_feature(env, ARM_FEATURE_EL2)
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|| arm_current_el(env) < 2 || arm_is_secure_below_el3(env);
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return !arm_is_el2_enabled(env) || arm_current_el(env) < 2;
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case ARM_CPU_MODE_MON:
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return arm_current_el(env) < 3;
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default:
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@ -12647,7 +12640,7 @@ int fp_exception_el(CPUARMState *env, int cur_el)
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/* CPTR_EL2 : present in v7VE or v8 */
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if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1)
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&& !arm_is_secure_below_el3(env)) {
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&& arm_is_el2_enabled(env)) {
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/* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */
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return 2;
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}
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