qemu/include/hw/riscv
Bin Meng b609b7e319 hw/riscv: Move sifive_uart model to hw/char
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_uart model to hw/char directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-09-09 15:54:19 -07:00
..
boot_opensbi.h riscv: Add opensbi firmware dynamic support 2020-07-13 17:25:37 -07:00
boot.h riscv: Add opensbi firmware dynamic support 2020-07-13 17:25:37 -07:00
microchip_pfsoc.h hw/riscv: microchip_pfsoc: Hook GPIO controllers 2020-09-09 15:54:19 -07:00
numa.h hw/riscv: Add helpers for RISC-V multi-socket NUMA machines 2020-08-25 09:11:35 -07:00
opentitan.h opentitan: Rename memmap enum constants 2020-08-27 14:04:54 -04:00
riscv_hart.h hw/riscv: hart: Add a new 'resetvec' property 2020-09-09 15:54:18 -07:00
sifive_cpu.h riscv: Add a sifive_cpu.h to include both E and U cpu type defines 2019-09-17 08:42:46 -07:00
sifive_e.h hw/riscv: Move sifive_gpio model to hw/gpio 2020-09-09 15:54:19 -07:00
sifive_test.h riscv: sifive_test: Add reset functionality 2019-09-17 08:42:44 -07:00
sifive_u.h hw/riscv: Move sifive_gpio model to hw/gpio 2020-09-09 15:54:19 -07:00
spike.h hw/riscv: spike: Allow creating multiple NUMA sockets 2020-08-25 09:11:35 -07:00
virt.h hw/riscv: virt: Allow creating multiple NUMA sockets 2020-08-25 09:11:35 -07:00