qemu/hw/riscv
Paolo Bonzini ca9b7e29de kconfig: add CONFIG_MSI_NONBROKEN
Not all interrupt controllers have a working implementation of
message-signalled interrupts; in some cases, the guest may expect
MSI to work but it won't due to the buggy or lacking emulation.

In QEMU this is represented by the "msi_nonbroken" variable.  This
patch adds a new configuration symbol enabled whenever the binary
contains an interrupt controller that will set "msi_nonbroken".  We
can then use it to remove devices that cannot be possibly added
to the machine, because they require MSI.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-03-18 09:39:57 +01:00
..
Kconfig kconfig: add CONFIG_MSI_NONBROKEN 2019-03-18 09:39:57 +01:00
Makefile.objs hw/riscv/Makefile.objs: Create CONFIG_* for riscv boards 2019-02-05 16:50:20 +01:00
riscv_hart.c riscv_hart: Fix crash when introspecting the device 2018-07-19 09:05:48 -07:00
riscv_htif.c hw: Do not include "exec/address-spaces.h" if it is not necessary 2018-06-01 14:15:10 +02:00
sifive_clint.c RISC-V: Fix CLINT timecmp low 32-bit writes 2018-12-20 12:08:43 -08:00
sifive_e.c riscv: Ensure the kernel start address is correctly cast 2019-02-11 15:56:22 -08:00
sifive_plic.c riscv: plic: Set msi_nonbroken as true 2019-03-18 09:39:57 +01:00
sifive_prci.c SiFive RISC-V PRCI Block 2018-03-07 08:30:28 +13:00
sifive_test.c SiFive RISC-V Test Finisher 2018-03-07 08:30:28 +13:00
sifive_u.c riscv: Ensure the kernel start address is correctly cast 2019-02-11 15:56:22 -08:00
sifive_uart.c sifive_uart: Implement interrupt pending register 2018-12-20 12:08:43 -08:00
spike.c riscv: Ensure the kernel start address is correctly cast 2019-02-11 15:56:22 -08:00
virt.c riscv: Ensure the kernel start address is correctly cast 2019-02-11 15:56:22 -08:00