b010980544
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4146 c046a42c-6fe2-441c-8c8c-71466251a162
615 lines
12 KiB
C
615 lines
12 KiB
C
/*
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* ARM micro operations
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2005-2007 CodeSourcery, LLC
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec.h"
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void OPPROTO op_addl_T0_T1_cc(void)
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{
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unsigned int src1;
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src1 = T0;
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T0 += T1;
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env->NZF = T0;
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env->CF = T0 < src1;
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env->VF = (src1 ^ T1 ^ -1) & (src1 ^ T0);
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}
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void OPPROTO op_adcl_T0_T1_cc(void)
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{
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unsigned int src1;
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src1 = T0;
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if (!env->CF) {
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T0 += T1;
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env->CF = T0 < src1;
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} else {
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T0 += T1 + 1;
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env->CF = T0 <= src1;
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}
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env->VF = (src1 ^ T1 ^ -1) & (src1 ^ T0);
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env->NZF = T0;
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FORCE_RET();
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}
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#define OPSUB(sub, sbc, res, T0, T1) \
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\
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void OPPROTO op_ ## sub ## l_T0_T1_cc(void) \
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{ \
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unsigned int src1; \
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src1 = T0; \
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T0 -= T1; \
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env->NZF = T0; \
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env->CF = src1 >= T1; \
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env->VF = (src1 ^ T1) & (src1 ^ T0); \
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res = T0; \
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} \
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\
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void OPPROTO op_ ## sbc ## l_T0_T1_cc(void) \
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{ \
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unsigned int src1; \
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src1 = T0; \
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if (!env->CF) { \
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T0 = T0 - T1 - 1; \
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env->CF = src1 > T1; \
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} else { \
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T0 = T0 - T1; \
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env->CF = src1 >= T1; \
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} \
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env->VF = (src1 ^ T1) & (src1 ^ T0); \
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env->NZF = T0; \
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res = T0; \
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FORCE_RET(); \
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}
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OPSUB(sub, sbc, T0, T0, T1)
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OPSUB(rsb, rsc, T0, T1, T0)
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void OPPROTO op_addq_T0_T1(void)
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{
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uint64_t res;
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res = ((uint64_t)T1 << 32) | T0;
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res += ((uint64_t)(env->regs[PARAM2]) << 32) | (env->regs[PARAM1]);
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T1 = res >> 32;
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T0 = res;
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}
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void OPPROTO op_addq_lo_T0_T1(void)
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{
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uint64_t res;
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res = ((uint64_t)T1 << 32) | T0;
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res += (uint64_t)(env->regs[PARAM1]);
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T1 = res >> 32;
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T0 = res;
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}
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/* Dual 16-bit accumulate. */
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void OPPROTO op_addq_T0_T1_dual(void)
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{
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uint64_t res;
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res = ((uint64_t)(env->regs[PARAM2]) << 32) | (env->regs[PARAM1]);
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res += (int32_t)T0;
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res += (int32_t)T1;
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env->regs[PARAM1] = (uint32_t)res;
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env->regs[PARAM2] = res >> 32;
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}
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/* Dual 16-bit subtract accumulate. */
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void OPPROTO op_subq_T0_T1_dual(void)
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{
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uint64_t res;
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res = ((uint64_t)(env->regs[PARAM2]) << 32) | (env->regs[PARAM1]);
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res += (int32_t)T0;
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res -= (int32_t)T1;
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env->regs[PARAM1] = (uint32_t)res;
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env->regs[PARAM2] = res >> 32;
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}
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void OPPROTO op_logicq_cc(void)
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{
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env->NZF = (T1 & 0x80000000) | ((T0 | T1) != 0);
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}
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/* memory access */
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#define MEMSUFFIX _raw
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#include "op_mem.h"
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#if !defined(CONFIG_USER_ONLY)
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#define MEMSUFFIX _user
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#include "op_mem.h"
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#define MEMSUFFIX _kernel
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#include "op_mem.h"
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#endif
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void OPPROTO op_clrex(void)
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{
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cpu_lock();
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helper_clrex(env);
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cpu_unlock();
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}
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/* T1 based, use T0 as shift count */
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void OPPROTO op_shll_T1_T0(void)
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{
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int shift;
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shift = T0 & 0xff;
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if (shift >= 32)
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T1 = 0;
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else
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T1 = T1 << shift;
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FORCE_RET();
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}
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void OPPROTO op_shrl_T1_T0(void)
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{
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int shift;
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shift = T0 & 0xff;
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if (shift >= 32)
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T1 = 0;
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else
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T1 = (uint32_t)T1 >> shift;
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FORCE_RET();
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}
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void OPPROTO op_sarl_T1_T0(void)
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{
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int shift;
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shift = T0 & 0xff;
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if (shift >= 32)
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shift = 31;
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T1 = (int32_t)T1 >> shift;
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}
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void OPPROTO op_rorl_T1_T0(void)
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{
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int shift;
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shift = T0 & 0x1f;
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if (shift) {
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T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
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}
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FORCE_RET();
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}
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/* T1 based, use T0 as shift count and compute CF */
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void OPPROTO op_shll_T1_T0_cc(void)
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{
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int shift;
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shift = T0 & 0xff;
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if (shift >= 32) {
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if (shift == 32)
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env->CF = T1 & 1;
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else
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env->CF = 0;
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T1 = 0;
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} else if (shift != 0) {
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env->CF = (T1 >> (32 - shift)) & 1;
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T1 = T1 << shift;
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}
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FORCE_RET();
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}
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void OPPROTO op_shrl_T1_T0_cc(void)
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{
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int shift;
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shift = T0 & 0xff;
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if (shift >= 32) {
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if (shift == 32)
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env->CF = (T1 >> 31) & 1;
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else
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env->CF = 0;
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T1 = 0;
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} else if (shift != 0) {
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env->CF = (T1 >> (shift - 1)) & 1;
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T1 = (uint32_t)T1 >> shift;
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}
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FORCE_RET();
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}
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void OPPROTO op_sarl_T1_T0_cc(void)
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{
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int shift;
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shift = T0 & 0xff;
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if (shift >= 32) {
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env->CF = (T1 >> 31) & 1;
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T1 = (int32_t)T1 >> 31;
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} else if (shift != 0) {
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env->CF = (T1 >> (shift - 1)) & 1;
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T1 = (int32_t)T1 >> shift;
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}
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FORCE_RET();
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}
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void OPPROTO op_rorl_T1_T0_cc(void)
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{
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int shift1, shift;
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shift1 = T0 & 0xff;
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shift = shift1 & 0x1f;
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if (shift == 0) {
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if (shift1 != 0)
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env->CF = (T1 >> 31) & 1;
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} else {
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env->CF = (T1 >> (shift - 1)) & 1;
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T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
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}
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FORCE_RET();
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}
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/* VFP support. We follow the convention used for VFP instrunctions:
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Single precition routines have a "s" suffix, double precision a
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"d" suffix. */
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#define VFP_OP(name, p) void OPPROTO op_vfp_##name##p(void)
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#define VFP_BINOP(name) \
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VFP_OP(name, s) \
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{ \
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FT0s = float32_ ## name (FT0s, FT1s, &env->vfp.fp_status); \
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} \
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VFP_OP(name, d) \
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{ \
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FT0d = float64_ ## name (FT0d, FT1d, &env->vfp.fp_status); \
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}
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VFP_BINOP(add)
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VFP_BINOP(sub)
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VFP_BINOP(mul)
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VFP_BINOP(div)
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#undef VFP_BINOP
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#define VFP_HELPER(name) \
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VFP_OP(name, s) \
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{ \
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do_vfp_##name##s(); \
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} \
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VFP_OP(name, d) \
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{ \
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do_vfp_##name##d(); \
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}
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VFP_HELPER(abs)
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VFP_HELPER(sqrt)
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VFP_HELPER(cmp)
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VFP_HELPER(cmpe)
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#undef VFP_HELPER
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/* XXX: Will this do the right thing for NANs. Should invert the signbit
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without looking at the rest of the value. */
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VFP_OP(neg, s)
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{
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FT0s = float32_chs(FT0s);
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}
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VFP_OP(neg, d)
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{
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FT0d = float64_chs(FT0d);
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}
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VFP_OP(F1_ld0, s)
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{
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union {
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uint32_t i;
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float32 s;
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} v;
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v.i = 0;
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FT1s = v.s;
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}
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VFP_OP(F1_ld0, d)
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{
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union {
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uint64_t i;
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float64 d;
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} v;
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v.i = 0;
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FT1d = v.d;
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}
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/* Helper routines to perform bitwise copies between float and int. */
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static inline float32 vfp_itos(uint32_t i)
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{
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union {
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uint32_t i;
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float32 s;
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} v;
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v.i = i;
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return v.s;
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}
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static inline uint32_t vfp_stoi(float32 s)
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{
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union {
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uint32_t i;
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float32 s;
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} v;
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v.s = s;
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return v.i;
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}
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static inline float64 vfp_itod(uint64_t i)
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{
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union {
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uint64_t i;
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float64 d;
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} v;
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v.i = i;
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return v.d;
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}
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static inline uint64_t vfp_dtoi(float64 d)
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{
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union {
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uint64_t i;
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float64 d;
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} v;
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v.d = d;
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return v.i;
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}
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/* Integer to float conversion. */
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VFP_OP(uito, s)
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{
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FT0s = uint32_to_float32(vfp_stoi(FT0s), &env->vfp.fp_status);
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}
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VFP_OP(uito, d)
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{
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FT0d = uint32_to_float64(vfp_stoi(FT0s), &env->vfp.fp_status);
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}
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VFP_OP(sito, s)
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{
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FT0s = int32_to_float32(vfp_stoi(FT0s), &env->vfp.fp_status);
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}
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VFP_OP(sito, d)
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{
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FT0d = int32_to_float64(vfp_stoi(FT0s), &env->vfp.fp_status);
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}
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/* Float to integer conversion. */
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VFP_OP(toui, s)
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{
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FT0s = vfp_itos(float32_to_uint32(FT0s, &env->vfp.fp_status));
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}
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VFP_OP(toui, d)
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{
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FT0s = vfp_itos(float64_to_uint32(FT0d, &env->vfp.fp_status));
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}
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VFP_OP(tosi, s)
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{
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FT0s = vfp_itos(float32_to_int32(FT0s, &env->vfp.fp_status));
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}
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VFP_OP(tosi, d)
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{
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FT0s = vfp_itos(float64_to_int32(FT0d, &env->vfp.fp_status));
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}
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/* TODO: Set rounding mode properly. */
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VFP_OP(touiz, s)
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{
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FT0s = vfp_itos(float32_to_uint32_round_to_zero(FT0s, &env->vfp.fp_status));
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}
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VFP_OP(touiz, d)
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{
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FT0s = vfp_itos(float64_to_uint32_round_to_zero(FT0d, &env->vfp.fp_status));
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}
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VFP_OP(tosiz, s)
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{
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FT0s = vfp_itos(float32_to_int32_round_to_zero(FT0s, &env->vfp.fp_status));
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}
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VFP_OP(tosiz, d)
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{
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FT0s = vfp_itos(float64_to_int32_round_to_zero(FT0d, &env->vfp.fp_status));
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}
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/* floating point conversion */
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VFP_OP(fcvtd, s)
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{
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FT0d = float32_to_float64(FT0s, &env->vfp.fp_status);
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}
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VFP_OP(fcvts, d)
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{
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FT0s = float64_to_float32(FT0d, &env->vfp.fp_status);
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}
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/* VFP3 fixed point conversion. */
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#define VFP_CONV_FIX(name, p, ftype, itype, sign) \
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VFP_OP(name##to, p) \
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{ \
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ftype tmp; \
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tmp = sign##int32_to_##ftype ((itype)vfp_##p##toi(FT0##p), \
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&env->vfp.fp_status); \
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FT0##p = ftype##_scalbn(tmp, PARAM1, &env->vfp.fp_status); \
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} \
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VFP_OP(to##name, p) \
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{ \
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ftype tmp; \
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tmp = ftype##_scalbn(FT0##p, PARAM1, &env->vfp.fp_status); \
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FT0##p = vfp_ito##p((itype)ftype##_to_##sign##int32_round_to_zero(tmp, \
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&env->vfp.fp_status)); \
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}
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VFP_CONV_FIX(sh, d, float64, int16, )
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VFP_CONV_FIX(sl, d, float64, int32, )
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VFP_CONV_FIX(uh, d, float64, uint16, u)
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VFP_CONV_FIX(ul, d, float64, uint32, u)
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VFP_CONV_FIX(sh, s, float32, int16, )
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VFP_CONV_FIX(sl, s, float32, int32, )
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VFP_CONV_FIX(uh, s, float32, uint16, u)
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VFP_CONV_FIX(ul, s, float32, uint32, u)
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/* Get and Put values from registers. */
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VFP_OP(getreg_F0, d)
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{
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FT0d = *(float64 *)((char *) env + PARAM1);
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}
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VFP_OP(getreg_F0, s)
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{
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FT0s = *(float32 *)((char *) env + PARAM1);
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}
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VFP_OP(getreg_F1, d)
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{
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FT1d = *(float64 *)((char *) env + PARAM1);
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}
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VFP_OP(getreg_F1, s)
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{
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FT1s = *(float32 *)((char *) env + PARAM1);
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}
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VFP_OP(setreg_F0, d)
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{
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*(float64 *)((char *) env + PARAM1) = FT0d;
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}
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VFP_OP(setreg_F0, s)
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{
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*(float32 *)((char *) env + PARAM1) = FT0s;
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}
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void OPPROTO op_vfp_movl_T0_fpscr(void)
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{
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do_vfp_get_fpscr ();
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}
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void OPPROTO op_vfp_movl_T0_fpscr_flags(void)
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{
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T0 = env->vfp.xregs[ARM_VFP_FPSCR] & (0xf << 28);
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}
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void OPPROTO op_vfp_movl_fpscr_T0(void)
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{
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do_vfp_set_fpscr();
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}
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void OPPROTO op_vfp_movl_T0_xreg(void)
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{
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T0 = env->vfp.xregs[PARAM1];
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}
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void OPPROTO op_vfp_movl_xreg_T0(void)
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{
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env->vfp.xregs[PARAM1] = T0;
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}
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/* Move between FT0s to T0 */
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void OPPROTO op_vfp_mrs(void)
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{
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T0 = vfp_stoi(FT0s);
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}
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void OPPROTO op_vfp_msr(void)
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{
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FT0s = vfp_itos(T0);
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}
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/* Move between FT0d and {T0,T1} */
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void OPPROTO op_vfp_mrrd(void)
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{
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CPU_DoubleU u;
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|
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u.d = FT0d;
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T0 = u.l.lower;
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T1 = u.l.upper;
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}
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void OPPROTO op_vfp_mdrr(void)
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|
{
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|
CPU_DoubleU u;
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|
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u.l.lower = T0;
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u.l.upper = T1;
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FT0d = u.d;
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}
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|
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/* Load immediate. PARAM1 is the 32 most significant bits of the value. */
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void OPPROTO op_vfp_fconstd(void)
|
|
{
|
|
CPU_DoubleU u;
|
|
u.l.upper = PARAM1;
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|
u.l.lower = 0;
|
|
FT0d = u.d;
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|
}
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|
|
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void OPPROTO op_vfp_fconsts(void)
|
|
{
|
|
FT0s = vfp_itos(PARAM1);
|
|
}
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|
|
|
void OPPROTO op_movl_cp_T0(void)
|
|
{
|
|
helper_set_cp(env, PARAM1, T0);
|
|
FORCE_RET();
|
|
}
|
|
|
|
void OPPROTO op_movl_T0_cp(void)
|
|
{
|
|
T0 = helper_get_cp(env, PARAM1);
|
|
FORCE_RET();
|
|
}
|
|
|
|
void OPPROTO op_movl_cp15_T0(void)
|
|
{
|
|
helper_set_cp15(env, PARAM1, T0);
|
|
FORCE_RET();
|
|
}
|
|
|
|
void OPPROTO op_movl_T0_cp15(void)
|
|
{
|
|
T0 = helper_get_cp15(env, PARAM1);
|
|
FORCE_RET();
|
|
}
|
|
|
|
void OPPROTO op_v7m_mrs_T0(void)
|
|
{
|
|
T0 = helper_v7m_mrs(env, PARAM1);
|
|
}
|
|
|
|
void OPPROTO op_v7m_msr_T0(void)
|
|
{
|
|
helper_v7m_msr(env, PARAM1, T0);
|
|
}
|
|
|
|
void OPPROTO op_movl_T0_sp(void)
|
|
{
|
|
if (PARAM1 == env->v7m.current_sp)
|
|
T0 = env->regs[13];
|
|
else
|
|
T0 = env->v7m.other_sp;
|
|
FORCE_RET();
|
|
}
|
|
|
|
#include "op_neon.h"
|
|
|
|
/* iwMMXt support */
|
|
#include "op_iwmmxt.c"
|