afb9539ebe
Tests for
packet semantics
vector loads (aligned and unaligned)
vector stores (aligned and unaligned)
vector masked stores
vector new value store
maximum HVX temps in a packet
vector operations
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
470 lines
14 KiB
C
470 lines
14 KiB
C
/*
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* Copyright(c) 2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <string.h>
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int err;
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static void __check(int line, int i, int j, uint64_t result, uint64_t expect)
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{
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if (result != expect) {
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printf("ERROR at line %d: [%d][%d] 0x%016llx != 0x%016llx\n",
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line, i, j, result, expect);
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err++;
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}
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}
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#define check(RES, EXP) __check(__LINE__, RES, EXP)
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#define MAX_VEC_SIZE_BYTES 128
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typedef union {
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uint64_t ud[MAX_VEC_SIZE_BYTES / 8];
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int64_t d[MAX_VEC_SIZE_BYTES / 8];
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uint32_t uw[MAX_VEC_SIZE_BYTES / 4];
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int32_t w[MAX_VEC_SIZE_BYTES / 4];
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uint16_t uh[MAX_VEC_SIZE_BYTES / 2];
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int16_t h[MAX_VEC_SIZE_BYTES / 2];
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uint8_t ub[MAX_VEC_SIZE_BYTES / 1];
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int8_t b[MAX_VEC_SIZE_BYTES / 1];
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} MMVector;
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#define BUFSIZE 16
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#define OUTSIZE 16
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#define MASKMOD 3
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MMVector buffer0[BUFSIZE] __attribute__((aligned(MAX_VEC_SIZE_BYTES)));
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MMVector buffer1[BUFSIZE] __attribute__((aligned(MAX_VEC_SIZE_BYTES)));
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MMVector mask[BUFSIZE] __attribute__((aligned(MAX_VEC_SIZE_BYTES)));
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MMVector output[OUTSIZE] __attribute__((aligned(MAX_VEC_SIZE_BYTES)));
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MMVector expect[OUTSIZE] __attribute__((aligned(MAX_VEC_SIZE_BYTES)));
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#define CHECK_OUTPUT_FUNC(FIELD, FIELDSZ) \
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static void check_output_##FIELD(int line, size_t num_vectors) \
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{ \
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for (int i = 0; i < num_vectors; i++) { \
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for (int j = 0; j < MAX_VEC_SIZE_BYTES / FIELDSZ; j++) { \
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__check(line, i, j, output[i].FIELD[j], expect[i].FIELD[j]); \
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} \
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} \
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}
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CHECK_OUTPUT_FUNC(d, 8)
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CHECK_OUTPUT_FUNC(w, 4)
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CHECK_OUTPUT_FUNC(h, 2)
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CHECK_OUTPUT_FUNC(b, 1)
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static void init_buffers(void)
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{
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int counter0 = 0;
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int counter1 = 17;
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for (int i = 0; i < BUFSIZE; i++) {
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for (int j = 0; j < MAX_VEC_SIZE_BYTES; j++) {
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buffer0[i].b[j] = counter0++;
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buffer1[i].b[j] = counter1++;
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}
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for (int j = 0; j < MAX_VEC_SIZE_BYTES / 4; j++) {
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mask[i].w[j] = (i + j % MASKMOD == 0) ? 0 : 1;
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}
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}
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}
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static void test_load_tmp(void)
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{
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void *p0 = buffer0;
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void *p1 = buffer1;
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void *pout = output;
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for (int i = 0; i < BUFSIZE; i++) {
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/*
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* Load into v12 as .tmp, then use it in the next packet
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* Should get the new value within the same packet and
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* the old value in the next packet
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*/
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asm("v3 = vmem(%0 + #0)\n\t"
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"r1 = #1\n\t"
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"v12 = vsplat(r1)\n\t"
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"{\n\t"
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" v12.tmp = vmem(%1 + #0)\n\t"
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" v4.w = vadd(v12.w, v3.w)\n\t"
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"}\n\t"
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"v4.w = vadd(v4.w, v12.w)\n\t"
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"vmem(%2 + #0) = v4\n\t"
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: : "r"(p0), "r"(p1), "r"(pout)
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: "r1", "v12", "v3", "v4", "v6", "memory");
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p0 += sizeof(MMVector);
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p1 += sizeof(MMVector);
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pout += sizeof(MMVector);
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for (int j = 0; j < MAX_VEC_SIZE_BYTES / 4; j++) {
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expect[i].w[j] = buffer0[i].w[j] + buffer1[i].w[j] + 1;
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}
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}
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check_output_w(__LINE__, BUFSIZE);
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}
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static void test_load_cur(void)
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{
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void *p0 = buffer0;
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void *pout = output;
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for (int i = 0; i < BUFSIZE; i++) {
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asm("{\n\t"
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" v2.cur = vmem(%0 + #0)\n\t"
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" vmem(%1 + #0) = v2\n\t"
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"}\n\t"
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: : "r"(p0), "r"(pout) : "v2", "memory");
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p0 += sizeof(MMVector);
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pout += sizeof(MMVector);
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for (int j = 0; j < MAX_VEC_SIZE_BYTES / 4; j++) {
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expect[i].uw[j] = buffer0[i].uw[j];
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}
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}
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check_output_w(__LINE__, BUFSIZE);
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}
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static void test_load_aligned(void)
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{
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/* Aligned loads ignore the low bits of the address */
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void *p0 = buffer0;
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void *pout = output;
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const size_t offset = 13;
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p0 += offset; /* Create an unaligned address */
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asm("v2 = vmem(%0 + #0)\n\t"
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"vmem(%1 + #0) = v2\n\t"
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: : "r"(p0), "r"(pout) : "v2", "memory");
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expect[0] = buffer0[0];
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check_output_w(__LINE__, 1);
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}
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static void test_load_unaligned(void)
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{
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void *p0 = buffer0;
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void *pout = output;
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const size_t offset = 12;
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p0 += offset; /* Create an unaligned address */
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asm("v2 = vmemu(%0 + #0)\n\t"
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"vmem(%1 + #0) = v2\n\t"
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: : "r"(p0), "r"(pout) : "v2", "memory");
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memcpy(expect, &buffer0[0].ub[offset], sizeof(MMVector));
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check_output_w(__LINE__, 1);
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}
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static void test_store_aligned(void)
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{
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/* Aligned stores ignore the low bits of the address */
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void *p0 = buffer0;
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void *pout = output;
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const size_t offset = 13;
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pout += offset; /* Create an unaligned address */
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asm("v2 = vmem(%0 + #0)\n\t"
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"vmem(%1 + #0) = v2\n\t"
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: : "r"(p0), "r"(pout) : "v2", "memory");
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expect[0] = buffer0[0];
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check_output_w(__LINE__, 1);
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}
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static void test_store_unaligned(void)
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{
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void *p0 = buffer0;
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void *pout = output;
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const size_t offset = 12;
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pout += offset; /* Create an unaligned address */
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asm("v2 = vmem(%0 + #0)\n\t"
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"vmemu(%1 + #0) = v2\n\t"
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: : "r"(p0), "r"(pout) : "v2", "memory");
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memcpy(expect, buffer0, 2 * sizeof(MMVector));
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memcpy(&expect[0].ub[offset], buffer0, sizeof(MMVector));
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check_output_w(__LINE__, 2);
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}
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static void test_masked_store(bool invert)
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{
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void *p0 = buffer0;
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void *pmask = mask;
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void *pout = output;
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memset(expect, 0xff, sizeof(expect));
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memset(output, 0xff, sizeof(expect));
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for (int i = 0; i < BUFSIZE; i++) {
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if (invert) {
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asm("r4 = #0\n\t"
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"v4 = vsplat(r4)\n\t"
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"v5 = vmem(%0 + #0)\n\t"
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"q0 = vcmp.eq(v4.w, v5.w)\n\t"
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"v5 = vmem(%1)\n\t"
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"if (!q0) vmem(%2) = v5\n\t" /* Inverted test */
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: : "r"(pmask), "r"(p0), "r"(pout)
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: "r4", "v4", "v5", "q0", "memory");
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} else {
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asm("r4 = #0\n\t"
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"v4 = vsplat(r4)\n\t"
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"v5 = vmem(%0 + #0)\n\t"
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"q0 = vcmp.eq(v4.w, v5.w)\n\t"
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"v5 = vmem(%1)\n\t"
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"if (q0) vmem(%2) = v5\n\t" /* Non-inverted test */
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: : "r"(pmask), "r"(p0), "r"(pout)
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: "r4", "v4", "v5", "q0", "memory");
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}
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p0 += sizeof(MMVector);
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pmask += sizeof(MMVector);
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pout += sizeof(MMVector);
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for (int j = 0; j < MAX_VEC_SIZE_BYTES / 4; j++) {
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if (invert) {
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if (i + j % MASKMOD != 0) {
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expect[i].w[j] = buffer0[i].w[j];
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}
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} else {
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if (i + j % MASKMOD == 0) {
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expect[i].w[j] = buffer0[i].w[j];
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}
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}
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}
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}
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check_output_w(__LINE__, BUFSIZE);
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}
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static void test_new_value_store(void)
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{
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void *p0 = buffer0;
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void *pout = output;
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asm("{\n\t"
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" v2 = vmem(%0 + #0)\n\t"
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" vmem(%1 + #0) = v2.new\n\t"
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"}\n\t"
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: : "r"(p0), "r"(pout) : "v2", "memory");
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expect[0] = buffer0[0];
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check_output_w(__LINE__, 1);
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}
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static void test_max_temps()
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{
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void *p0 = buffer0;
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void *pout = output;
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asm("v0 = vmem(%0 + #0)\n\t"
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"v1 = vmem(%0 + #1)\n\t"
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"v2 = vmem(%0 + #2)\n\t"
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"v3 = vmem(%0 + #3)\n\t"
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"v4 = vmem(%0 + #4)\n\t"
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"{\n\t"
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" v1:0.w = vadd(v3:2.w, v1:0.w)\n\t"
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" v2.b = vshuffe(v3.b, v2.b)\n\t"
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" v3.w = vadd(v1.w, v4.w)\n\t"
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" v4.tmp = vmem(%0 + #5)\n\t"
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"}\n\t"
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"vmem(%1 + #0) = v0\n\t"
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"vmem(%1 + #1) = v1\n\t"
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"vmem(%1 + #2) = v2\n\t"
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"vmem(%1 + #3) = v3\n\t"
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"vmem(%1 + #4) = v4\n\t"
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: : "r"(p0), "r"(pout) : "memory");
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/* The first two vectors come from the vadd-pair instruction */
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for (int i = 0; i < MAX_VEC_SIZE_BYTES / 4; i++) {
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expect[0].w[i] = buffer0[0].w[i] + buffer0[2].w[i];
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expect[1].w[i] = buffer0[1].w[i] + buffer0[3].w[i];
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}
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/* The third vector comes from the vshuffe instruction */
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for (int i = 0; i < MAX_VEC_SIZE_BYTES / 2; i++) {
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expect[2].uh[i] = (buffer0[2].uh[i] & 0xff) |
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(buffer0[3].uh[i] & 0xff) << 8;
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}
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/* The fourth vector comes from the vadd-single instruction */
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for (int i = 0; i < MAX_VEC_SIZE_BYTES / 4; i++) {
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expect[3].w[i] = buffer0[1].w[i] + buffer0[5].w[i];
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}
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/*
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* The fifth vector comes from the load to v4
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* make sure the .tmp is dropped
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*/
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expect[4] = buffer0[4];
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check_output_b(__LINE__, 5);
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}
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#define VEC_OP1(ASM, EL, IN, OUT) \
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asm("v2 = vmem(%0 + #0)\n\t" \
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"v2" #EL " = " #ASM "(v2" #EL ")\n\t" \
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"vmem(%1 + #0) = v2\n\t" \
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: : "r"(IN), "r"(OUT) : "v2", "memory")
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#define VEC_OP2(ASM, EL, IN0, IN1, OUT) \
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asm("v2 = vmem(%0 + #0)\n\t" \
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"v3 = vmem(%1 + #0)\n\t" \
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"v2" #EL " = " #ASM "(v2" #EL ", v3" #EL ")\n\t" \
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"vmem(%2 + #0) = v2\n\t" \
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: : "r"(IN0), "r"(IN1), "r"(OUT) : "v2", "v3", "memory")
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#define TEST_VEC_OP1(NAME, ASM, EL, FIELD, FIELDSZ, OP) \
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static void test_##NAME(void) \
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{ \
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void *pin = buffer0; \
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void *pout = output; \
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for (int i = 0; i < BUFSIZE; i++) { \
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VEC_OP1(ASM, EL, pin, pout); \
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pin += sizeof(MMVector); \
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pout += sizeof(MMVector); \
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} \
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for (int i = 0; i < BUFSIZE; i++) { \
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for (int j = 0; j < MAX_VEC_SIZE_BYTES / FIELDSZ; j++) { \
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expect[i].FIELD[j] = OP buffer0[i].FIELD[j]; \
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} \
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} \
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check_output_##FIELD(__LINE__, BUFSIZE); \
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}
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#define TEST_VEC_OP2(NAME, ASM, EL, FIELD, FIELDSZ, OP) \
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static void test_##NAME(void) \
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{ \
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void *p0 = buffer0; \
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void *p1 = buffer1; \
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void *pout = output; \
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for (int i = 0; i < BUFSIZE; i++) { \
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VEC_OP2(ASM, EL, p0, p1, pout); \
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p0 += sizeof(MMVector); \
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p1 += sizeof(MMVector); \
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pout += sizeof(MMVector); \
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} \
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for (int i = 0; i < BUFSIZE; i++) { \
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for (int j = 0; j < MAX_VEC_SIZE_BYTES / FIELDSZ; j++) { \
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expect[i].FIELD[j] = buffer0[i].FIELD[j] OP buffer1[i].FIELD[j]; \
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} \
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} \
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check_output_##FIELD(__LINE__, BUFSIZE); \
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}
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#define THRESHOLD 31
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#define PRED_OP2(ASM, IN0, IN1, OUT, INV) \
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asm("r4 = #%3\n\t" \
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"v1.b = vsplat(r4)\n\t" \
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"v2 = vmem(%0 + #0)\n\t" \
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"q0 = vcmp.gt(v2.b, v1.b)\n\t" \
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"v3 = vmem(%1 + #0)\n\t" \
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"q1 = vcmp.gt(v3.b, v1.b)\n\t" \
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"q2 = " #ASM "(q0, " INV "q1)\n\t" \
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"r4 = #0xff\n\t" \
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"v1.b = vsplat(r4)\n\t" \
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"if (q2) vmem(%2 + #0) = v1\n\t" \
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: : "r"(IN0), "r"(IN1), "r"(OUT), "i"(THRESHOLD) \
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: "r4", "v1", "v2", "v3", "q0", "q1", "q2", "memory")
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#define TEST_PRED_OP2(NAME, ASM, OP, INV) \
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static void test_##NAME(bool invert) \
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{ \
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void *p0 = buffer0; \
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void *p1 = buffer1; \
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void *pout = output; \
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memset(output, 0, sizeof(expect)); \
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for (int i = 0; i < BUFSIZE; i++) { \
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PRED_OP2(ASM, p0, p1, pout, INV); \
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p0 += sizeof(MMVector); \
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p1 += sizeof(MMVector); \
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pout += sizeof(MMVector); \
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} \
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for (int i = 0; i < BUFSIZE; i++) { \
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for (int j = 0; j < MAX_VEC_SIZE_BYTES; j++) { \
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bool p0 = (buffer0[i].b[j] > THRESHOLD); \
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bool p1 = (buffer1[i].b[j] > THRESHOLD); \
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if (invert) { \
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expect[i].b[j] = (p0 OP !p1) ? 0xff : 0x00; \
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} else { \
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expect[i].b[j] = (p0 OP p1) ? 0xff : 0x00; \
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} \
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} \
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} \
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check_output_b(__LINE__, BUFSIZE); \
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}
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TEST_VEC_OP2(vadd_w, vadd, .w, w, 4, +)
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TEST_VEC_OP2(vadd_h, vadd, .h, h, 2, +)
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TEST_VEC_OP2(vadd_b, vadd, .b, b, 1, +)
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TEST_VEC_OP2(vsub_w, vsub, .w, w, 4, -)
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TEST_VEC_OP2(vsub_h, vsub, .h, h, 2, -)
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TEST_VEC_OP2(vsub_b, vsub, .b, b, 1, -)
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TEST_VEC_OP2(vxor, vxor, , d, 8, ^)
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TEST_VEC_OP2(vand, vand, , d, 8, &)
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TEST_VEC_OP2(vor, vor, , d, 8, |)
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TEST_VEC_OP1(vnot, vnot, , d, 8, ~)
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TEST_PRED_OP2(pred_or, or, |, "")
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TEST_PRED_OP2(pred_or_n, or, |, "!")
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TEST_PRED_OP2(pred_and, and, &, "")
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TEST_PRED_OP2(pred_and_n, and, &, "!")
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TEST_PRED_OP2(pred_xor, xor, ^, "")
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int main()
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{
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init_buffers();
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test_load_tmp();
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test_load_cur();
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test_load_aligned();
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test_load_unaligned();
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test_store_aligned();
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test_store_unaligned();
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test_masked_store(false);
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test_masked_store(true);
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test_new_value_store();
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test_max_temps();
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test_vadd_w();
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test_vadd_h();
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test_vadd_b();
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test_vsub_w();
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test_vsub_h();
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test_vsub_b();
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test_vxor();
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test_vand();
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test_vor();
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test_vnot();
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test_pred_or(false);
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test_pred_or_n(true);
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test_pred_and(false);
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test_pred_and_n(true);
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test_pred_xor(false);
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puts(err ? "FAIL" : "PASS");
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return err ? 1 : 0;
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}
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