qemu/tests/tcg/hexagon
Taylor Simpson afb9539ebe Hexagon HVX (tests/tcg/hexagon) hvx_misc test
Tests for
    packet semantics
    vector loads (aligned and unaligned)
    vector stores (aligned and unaligned)
    vector masked stores
    vector new value store
    maximum HVX temps in a packet
    vector operations

Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-11-03 16:01:37 -05:00
..
atomics.c
brev.c Hexagon (target/hexagon) bit reverse (brev) addressing 2021-05-01 16:03:10 -07:00
circ.c Hexagon (target/hexagon) circular addressing 2021-05-01 16:01:39 -07:00
dual_stores.c
first.S
float_convs.ref
float_madds.ref
fpstuff.c Hexagon (target/hexagon) add F2_sfinvsqrta 2021-05-01 08:31:43 -07:00
hex_sigsegv.c Hexagon (target/hexagon) probe the stores in a packet at start of commit 2021-10-06 10:29:11 -05:00
hvx_misc.c Hexagon HVX (tests/tcg/hexagon) hvx_misc test 2021-11-03 16:01:37 -05:00
load_align.c Hexagon (target/hexagon) load into shifted register instructions 2021-05-01 16:06:11 -07:00
load_unpack.c Hexagon (target/hexagon) load and unpack bytes instructions 2021-05-01 16:06:09 -07:00
Makefile.target Hexagon (target/hexagon) put writes to USR into temp until commit 2021-10-28 22:22:49 -05:00
mem_noshuf.c
misc.c Hexagon (target/hexagon) fix l2fetch instructions 2021-06-29 11:32:50 -05:00
multi_result.c Hexagon (target/hexagon) add A4_addp_c/A4_subp_c 2021-05-01 08:31:43 -07:00
overflow.c Hexagon (target/hexagon) put writes to USR into temp until commit 2021-10-28 22:22:49 -05:00
preg_alias.c
vector_add_int.c Hexagon HVX (tests/tcg/hexagon) vector_add_int test 2021-11-03 16:01:37 -05:00