Bin Meng 933f73f13e hw/riscv: microchip_pfsoc: Connect DDR memory controller modules ... Connect DDR SGMII PHY module and CFG module to the PolarFire SoC. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1603863010-15807-4-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2020-11-03 07:17:23 -08:00
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boot_opensbi.h	riscv: Add opensbi firmware dynamic support	2020-07-13 17:25:37 -07:00
boot.h	hw/riscv: Load the kernel after the firmware	2020-10-22 12:00:22 -07:00
microchip_pfsoc.h	hw/riscv: microchip_pfsoc: Connect DDR memory controller modules	2020-11-03 07:17:23 -08:00
numa.h	hw/riscv: Add helpers for RISC-V multi-socket NUMA machines	2020-08-25 09:11:35 -07:00
opentitan.h	Use OBJECT_DECLARE_SIMPLE_TYPE when possible	2020-09-18 14:12:32 -04:00
riscv_hart.h	Use OBJECT_DECLARE_SIMPLE_TYPE when possible	2020-09-18 14:12:32 -04:00
sifive_cpu.h	riscv: Add a sifive_cpu.h to include both E and U cpu type defines	2019-09-17 08:42:46 -07:00
sifive_e.h	sifive_e: Rename memmap enum constants	2020-09-18 13:49:48 -04:00
sifive_u.h	hw/riscv: sifive_u: Allow specifying the CPU	2020-10-22 12:00:22 -07:00
spike.h	Use DECLARE_*CHECKER* macros	2020-09-09 09:27:09 -04:00
virt.h	Use DECLARE_*CHECKER* macros	2020-09-09 09:27:09 -04:00