qemu/target
Philipp Tomsich a1095bdcb0 target/riscv: Add rev8 instruction, removing grev/grevi
The 1.0.0 version of Zbb does not contain grev/grevi.  Instead, a
rev8 instruction (equivalent to the rev8 pseudo-instruction built on
grevi from pre-0.93 draft-B) is available.

This commit adds the new rev8 instruction and removes grev/grevi.

Note that there is no W-form of this instruction (both a
sign-extending and zero-extending 32-bit version can easily be
synthesized by following rev8 with either a srai or srli instruction
on RV64) and that the opcode encodings for rev8 in RV32 and RV64 are
different.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210911140016.834071-14-philipp.tomsich@vrull.eu
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-07 08:41:33 +10:00
..
alpha hw/core: Make do_unaligned_access noreturn 2021-09-21 19:36:44 -07:00
arm tcg: Rename TCGMemOpIdx to MemOpIdx 2021-10-05 16:53:17 -07:00
avr include/exec: Move cpu_signal_handler declaration 2021-09-21 19:36:44 -07:00
cris include/exec: Move cpu_signal_handler declaration 2021-09-21 19:36:44 -07:00
hexagon target/hexagon: Use tcg_constant_* 2021-10-06 10:29:56 -05:00
hppa hw/core: Make do_unaligned_access noreturn 2021-09-21 19:36:44 -07:00
i386 tcg: Rename TCGMemOpIdx to MemOpIdx 2021-10-05 16:53:17 -07:00
m68k tcg: Rename TCGMemOpIdx to MemOpIdx 2021-10-05 16:53:17 -07:00
microblaze hw/core: Make do_unaligned_access noreturn 2021-09-21 19:36:44 -07:00
mips tcg: Rename TCGMemOpIdx to MemOpIdx 2021-10-05 16:53:17 -07:00
nios2 hw/core: Make do_unaligned_access noreturn 2021-09-21 19:36:44 -07:00
openrisc include/exec: Move cpu_signal_handler declaration 2021-09-21 19:36:44 -07:00
ppc target/ppc: Check privilege level based on PSR and LPCR[HR] in tlbie[l] 2021-09-30 12:26:06 +10:00
riscv target/riscv: Add rev8 instruction, removing grev/grevi 2021-10-07 08:41:33 +10:00
rx include/exec: Move cpu_signal_handler declaration 2021-09-21 19:36:44 -07:00
s390x tcg: Rename TCGMemOpIdx to MemOpIdx 2021-10-05 16:53:17 -07:00
sh4 target/sh4: Use lookup_symbol in sh4_tr_disas_log 2021-10-04 09:47:26 +02:00
sparc tcg: Rename TCGMemOpIdx to MemOpIdx 2021-10-05 16:53:17 -07:00
tricore include/exec: Move cpu_signal_handler declaration 2021-09-21 19:36:44 -07:00
xtensa target/xtensa: list cores in a text file 2021-10-05 13:10:29 +02:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
meson.build Drop the deprecated unicore32 target 2021-05-12 18:20:52 +02:00